Signal restoration circuit, latency adjustment circuit, memory controller, processor, computer, signal restoration method, and latency adjustment method

• US 8,788,780 B2
• Filed: 05/16/2012
• Issued: 07/22/2014
• Est. Priority Date: 12/25/2009
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Tokuhiro, Noriyuki, Takahashi, Noriyuki, Aiso, Shinya
• Primary Examiner(s): Gu, Shawn X
• Application Number:
  US13/472,575
• Publication Number:
  US 20120226884A1
• Time in Patent Office: 797 Days
• Field of Search: 711/167
• US Class Current: 711/167
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2207/2272 Latency related aspects
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A signal restoration circuit includes a storage configured to store input signals by disposing the input signals in an input order, the input signals being readable from the storage in the disposed order, and a storage controller configured to control delay time from an input of the input signal to an output in the storage based on delay information of the input signal.

Claims

1. A signal restoration circuit comprising:

a storage configured to store input signals by disposing the input signals in an input order, the input signals being readable from the storage in the disposed order; and

a storage controller configured to control delay time from an input of the input signals to an output in the storage based on delay information,

wherein the delay information is attached to each of the input signals and quantitatively represents a delay clock time of each of the input signals.

2. The signal restoration circuit as claimed in claim 1, wherein

when a delay amount of the input signals is large, the storage controller reduces the delay time, and when the delay amount of the input signals is small, the storage controller increases the delay time.

3. The signal restoration circuit as claimed in claim 1, wherein

the storage controller receives the delay information of the input signals, and reads the input signals from the storage in the disposed order based on the delay information, and wherein

when the delay information is constant, the storage controller causes the storage to store the input signals in the input order, or when the delay information transitions, the storage controller selects positions of the disposed input signals based on the transition to cause the storage to store the input signals at the selected positions.

4. The signal restoration circuit as claimed in claim 1, further comprising:

a delay information detecting part configured to compare the input signals and a reference clock signal, and detect a delay amount of the input signals corresponding to the reference clock signal.

5. The signal restoration circuit as claimed in claim 4, further comprising:

an offset delay amount measuring part configured to measure an offset delay amount of a received signal corresponding to a transmitted delay measuring signal, wherein

the storage controller generates the delay information including the offset delay amount and the delay amount detected by the delay information detecting part.

6. The signal restoration circuit as claimed in claim 1, wherein

the input signals are data signals received from a memory.

7. The signal restoration circuit as claimed in claim 1, wherein

the storage is a first-in first-out (FIFO) capable circuit formed of two or more flipflops, and identical data are input to two adjacent flip-flops.

8. A latency adjustment circuit comprising:

the signal restoration circuit as claimed in claim 1, wherein

latency of read data in each of memory devices is adjusted by utilizing the signal restoration circuit.

9. A memory controller comprising:

the latency adjustment circuit as claimed in claim 8.

10. A processor comprising:

the latency adjustment circuit as claimed in claim 8.

11. A computer comprising:

the latency adjustment circuit as claimed in claim 8.

12. A processor, comprising:

a memory controller, said memory controller comprising the latency adjustment circuit recited in claim 8.

13. A computer, comprising:

a memory controller, said memory controller comprising the latency adjustment circuit as claimed in claim 8.

14. A computer, comprising:

a processor, said processor comprising the latency adjustment circuit as claimed in claim 8.

15. A signal restoration method comprising:

storing input signals in a storage by disposing the input signals in an input order, the stored input signals being readable from the storage in the disposed order; and

controlling a delay time from an input of the input signals to an output in the storage based on delay information,

wherein the delay information is attached to each of the input signals and quantitatively represents a delay clock time of each of the input signals.

16. The signal restoration method as claimed in claim 15, further comprising:

receiving the delay information of the input signals and reading the input signals in the disposed order from the storage based on the delay information; and

storing, when the delay information is constant, the input signals in the input order, or selecting, when the delay information transitions, positions of the disposed input signals based on the transition to store the input signals at the selected positions.

17. The signal restoration method as claimed in claim 15, further comprising:

comparing the input signals and a reference clock signal, and detecting, by a delay amount detecting part, a delay amount of the input signals corresponding to the reference clock signal.

18. The signal restoration method as claimed in claim 17, further comprising:

measuring an offset amount of a received signal corresponding to a transmitted delay measuring signal; and

generating the delay information based on the offset amount and the delay amount detected by the delay amount detecting part, and changing positions of the stored input signals based on the delay information.

19. A latency adjustment method comprising:

the signal restoration method as claimed in claim 15 to adjust latency of read data in each of memory devices.