Flash memory device error correction code controllers and related methods and memory systems

• US 8,788,905 B2
• Filed: 01/25/2011
• Issued: 07/22/2014
• Est. Priority Date: 01/08/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Chang-Duck, Heo, Seok-won, Park, Si-Yung, Lee, Dong-Ryoul
• Primary Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US13/012,955
• Publication Number:
  US 20110119560A1
• Time in Patent Office: 1,274 Days
• Field of Search: 714/763, 365/185.09, 365/185.33
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: H03M 13/15 Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes H03M13/17 takes precedence
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
• CPC Class Codes: H03M 13/23 using convolutional codes, e.g. unit memory codes
• CPC Class Codes: H03M 13/35 Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
• CPC Class Codes: H03M 13/3715 Adaptation to the number of estimated errors or to the channel state

Abstract

An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.

Claims

1. An error correction code (ECC) controller for a memory device having a memory cell array that stores M-bit data per memory cell of a main cell area of the memory cell array, M being a positive integer equal to or greater than 2, the ECC controller comprising:

an encoder that is configured to generate first ECC data in response to input data that is stored in the main cell area of the memory cell array using a first error correction scheme and that is configured to generate second ECC data in response to the input data using a second error correction scheme,

wherein the first error correction scheme operates at a higher speed than the second error correction scheme, and wherein the second error correction scheme is capable of correcting a greater number of errors than the first error correction scheme.

2. The ECC controller of claim 1, wherein the encoder is configured to store the first ECC data and the second ECC data in the memory cell array.

3. The ECC controller of claim 2, wherein the memory cell array further includes a spare area, and wherein the first ECC data and the second ECC data are stored in the spare area of the memory cell array.

4. The ECC controller of claim 3, wherein the first and second ECC data are stored by storing 1-bit of data per memory cell.

5. The ECC controller of claim 1, wherein the encoder comprises:

a first encoder that is configured to generate the first ECC data using the first error correction scheme; and

a second encoder that is configured to generate the second ECC data using the second error correction scheme.

6. The ECC controller of claim 5, further comprising a decoder that is configured to correct errors in the input data when the input data is read from the memory device.

7. The ECC controller of claim 6, wherein the decoder comprises:

a first decoder that is configured to correct errors in the read input data using the first ECC data;

a second decoder that is configured to correct errors in the read input data using the second ECC data.

8. The ECC controller of claim 6, wherein the decoder is further configured to correct errors in the input data using the first ECC data when the input data contains less than a threshold number of detected errors and to correct errors in the input data using the second ECC data when the input data contains a number of detected errors equal to or more than the threshold number of detected errors.

9. The ECC controller of claim 1, in combination with the flash memory device to form a memory system.

10. The ECC controller of claim 1, wherein the encoder uses the same input data to generate the first ECC data and the second ECC data.

11. A method for error correction encoding first data that is to be stored in a non-volatile memory device, the method comprising:

generating first error correction code (ECC) data for the first data using a first error correction scheme;

generating second error correction code (ECC) data for the first data using a second error correction scheme;

storing the first data, the first ECC data, and the second ECC in the non-volatile memory device;

reading the first data from the non-volatile memory device;

selecting one of the first ECC data or the second ECC data to correct the errors in the first data based on whether a number of errors in the first data is less than a threshold number of errors; and

correcting the errors in the first data using the selected one of the first ECC data or the second ECC data.

12. The method of claim 11, wherein storing the first data, the first ECC data and the second ECC data in the non-volatile memory device comprises storing the first data in a first region of a memory cell array of the non-volatile memory device, where multiple bits of the first data are stored in at least some of the memory cells of the first region, and storing the first and second ECC data in a second region of the memory cell array, where a single bit of data is stored in each of the memory cells of the second region.

13. The method of claim 11, wherein the first error correction scheme operates at a higher speed than the second error correction scheme, and wherein the second error correction scheme is capable of correcting a greater number of errors than the first error correction scheme.

14. The method of claim 11, wherein the first error correction scheme is an error correction scheme that uses a Bose-Chaudhuri-Hocquenghem (BCH) code, and wherein the second error correction scheme is an error correction scheme that uses a Reed Solomon (RS) code.

15. A memory system comprising:

a flash memory device that is configured to store M-bit data, M being a positive integer equal to or greater than 2; and

a memory controller that is configured to control the flash memory device, the memory controller comprising an encoder that is configured to generate first ECC data in response to input data that is stored in the flash memory device by using a first error correction scheme and that is configured to generate second ECC data in response to the input data by using a second error correction scheme, the input data, the first ECC data, and the second ECC data being stored in the flash memory device.

16. The memory system of claim 15, the memory controller further comprising a decoder that is configured to correct errors in the input data when the input data is read from the flash memory device using one of the first ECC data or the second ECC data.

17. The memory system of claim 16, wherein the encoder comprises:

a first encoder that is configured to generate the first ECC data in response to the input data by using the first error correction scheme; and

a second encoder that is configured to generate the second ECC data in response to the input data by using the second error correction scheme.

18. The memory system of claim 16, wherein the decoder comprises:

a first decoder that is configured to correct the errors in the read input data using the first ECC data; and

a second decoder that is configured to correct the errors in the read input data using the second ECC data.

19. The memory system of claim 15, wherein the first error correction scheme is an error correction scheme that uses a Bose-Chaudhuri-Hocquenghem (BCH) code, and the second error correction scheme is an error correction scheme that uses a Reed Solomon (RS) code.

20. The memory system of claim 15, wherein a memory cell array of the flash memory device includes a data area and a spare area, and wherein the input data is stored in the data area, and wherein the first ECC data and the second ECC data are stored in the spare area.

21. The memory system of claim 15, wherein the encoder uses the same input data to generate the first ECC data and the second ECC data.