Semiconductor device and method for manufacturing the same

• US 8,790,961 B2
• Filed: 12/17/2012
• Issued: 07/29/2014
• Est. Priority Date: 12/23/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sasagawa, Shinya, Suzawa, Hideomi
• Primary Examiner(s): Blum, David S
• Application Number:
  US13/716,891
• Publication Number:
  US 20130161605A1
• Time in Patent Office: 589 Days
• Field of Search: 438/104, 257/E21.411, 257/E29.242
• US Class Current: 438/104
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A bottom-gate transistor with a short channel length and a method for manufacturing the transistor are provided. A bottom-gate transistor with a short channel length in which portions of a source electrode and a drain electrode which are proximate to a channel formation region are thinner than other portions thereof was devised. In addition, the portions of the source electrode and the drain electrode which are proximate to the channel formation region are formed in a later step than the other portions thereof, whereby a bottom-gate transistor with a short channel length can be manufactured.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer;

forming a gate insulating layer over the gate electrode layer;

forming a semiconductor layer over the gate insulating layer;

forming a first conductive layer over the semiconductor layer;

forming a second conductive layer over the first conductive layer so that the first conductive layer is exposed in a region which overlaps with a channel formation region of the semiconductor layer;

forming a protective layer over the second conductive layer;

forming a hard mask layer over the protective layer;

forming a resist pattern over the hard mask layer, the resist pattern including an opening which overlaps with the semiconductor layer;

etching the hard mask layer using the resist pattern;

etching the protective layer using the hard mask layer; and

etching the first conductive layer using the hard mask layer.

2. The method for manufacturing the semiconductor device according to claim 1,

wherein the semiconductor layer includes an oxide including indium and zinc.

3. The method for manufacturing the semiconductor device according to claim 1, wherein the opening in the resist pattern is formed by an electron beam.

4. The method for manufacturing the semiconductor device according to claim 1, wherein the hard mask layer comprises amorphous silicon.

5. The method for manufacturing the semiconductor device according to claim 1, wherein a channel length of a transistor including the semiconductor layer is greater than or equal to 20 nm and less than or equal to 100 nm.

6. The method for manufacturing the semiconductor device according to claim 1, wherein a length of the semiconductor layer in a channel length direction is larger than a length of the gate electrode layer in the channel length direction.

7. The method for manufacturing the semiconductor device according to claim 1, further comprising the step of planarizing the gate insulating layer before forming the semiconductor layer.

8. The method for manufacturing the semiconductor device according to claim 1, further comprising the step of planarizing the protective layer before forming the hard mask layer.

9. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer;

forming a gate insulating layer over the gate electrode layer;

forming a semiconductor layer over the gate insulating layer;

forming a first conductive layer over the semiconductor layer;

forming a second conductive layer over the first conductive layer;

forming a protective layer over the second conductive layer;

forming a first resist pattern over the protective layer, the first resist pattern including a first opening;

etching the protective layer and the second conductive layer using the first resist pattern;

forming, after the step of etching, a second resist pattern over the first conductive layer and the protective layer, the second resist pattern including a second opening in a region which overlaps with the semiconductor layer; and

etching the first conductive layer using the second resist pattern.

10. The method for manufacturing the semiconductor device according to claim 9,

wherein the semiconductor layer includes an oxide including indium and zinc.

11. The method for manufacturing the semiconductor device according to claim 9, wherein the second opening is formed by an electron beam.

12. The method for manufacturing the semiconductor device according to claim 9, wherein a channel length of a transistor including the semiconductor layer is greater than or equal to 20 nm and less than or equal to 100 nm.

13. The method for manufacturing the semiconductor device according to claim 9, wherein a length of the semiconductor layer in a channel length direction is larger than a length of the gate electrode layer in the channel length direction.

14. The method for manufacturing the semiconductor device according to claim 9, further comprising the step of planarizing the gate insulating layer before forming the semiconductor layer.

15. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer;

forming a first conductive layer over the oxide semiconductor layer;

forming a second conductive layer over the first conductive layer so that the first conductive layer is exposed in a region which overlaps with a channel formation region of the oxide semiconductor layer;

forming a protective layer over the second conductive layer;

forming a hard mask layer over the protective layer;

forming a resist pattern over the hard mask layer, the resist pattern including an opening which overlaps with the oxide semiconductor layer;

etching the hard mask layer using the resist pattern;

etching the protective layer using the hard mask layer; and

etching the first conductive layer using the hard mask layer.

16. The method for manufacturing the semiconductor device according to claim 15,

wherein the oxide semiconductor layer includes indium and zinc.

17. The method for manufacturing the semiconductor device according to claim 15, wherein the opening in the resist pattern is formed by an electron beam.

18. The method for manufacturing the semiconductor device according to claim 15, wherein the hard mask layer comprises amorphous silicon.

19. The method for manufacturing the semiconductor device according to claim 15, wherein a channel length of a transistor including the oxide semiconductor layer is greater than or equal to 20 nm and less than or equal to 100 nm.

20. The method for manufacturing the semiconductor device according to claim 15, further comprising the step of planarizing the protective layer before forming the hard mask layer.