Doping of semiconductor fin devices

• US 8,790,970 B2
• Filed: 06/05/2006
• Issued: 07/29/2014
• Est. Priority Date: 04/29/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeo, Yee-Chia, Wang, Ping-Wei, Chen, Hao-Yu, Yang, Fu-Liang, Hu, Chenming
• Primary Examiner(s): WOLDEGEORGIS, ERMIAS T
• Application Number:
  US11/446,697
• Publication Number:
  US 20060234431A1
• Time in Patent Office: 2,976 Days
• Field of Search: 257/302, 257/255, 257/347, 257/350, 257/351, 257/527, 257/627, 257/628, 257/E21.345, 257/E21.703, 257/E27.112, 257/E29.004, 438/151, 438/157, 438/164, 438/283, 438/514, 438/525
• US Class Current: 438/197
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

Claims

1. A method of doping semiconductor fins of multiple-gate transistors, the method comprising:

providing a semiconductor structure comprising of a plurality of semiconductor fins overlying an insulator layer, each fin having a gate dielectric overlying a portion of that semiconductor fin, and a gate electrode overlying said gate dielectric, each of the semiconductor fins having a channel region of a first conductivity type disposed beneath the gate electrode, the channel region located in a top surface, a first sidewall surface, and a second sidewall surface of the semiconductor fin; and

forming a source region and/or drain region comprising;

implanting dopant ions of an opposite second conductivity type in the first sidewall surface and in the top surface at an angle α

to dope along the first sidewall surface and along the top surface, the angle α

being between 26 degrees and about 63 degrees with respect to the normal of the top surface and being in a first plane perpendicular to the first sidewall surface, the normal of the top surface being in the first plane; and

implanting dopant ions of the second conductivity type in the second sidewall surface and in the top surface at an angle β

to dope along the second sidewall surface and along the top surface, the angle β

being between 26 degrees and about 63 degrees with respect to the normal of the top surface and being in a second plane perpendicular to the second sidewall surface, the normal of the top surface being in the second plane.

2. The method of claim 1 wherein the semiconductor fins comprise silicon fins.

3. The method of claim 2 wherein the dopant ions are p-type dopant ions selected from the group consisting of boron and indium and combinations thereof.

4. The method of claim 3 wherein the first and second sidewall surfaces are (110) crystallographic surfaces.

5. The method of claim 2 wherein the dopant ions are n-type dopant ions selected from the group consisting of phosphorus, arsenic, and antimony and combinations thereof.

6. The method of claim 5 wherein the first and second sidewall surfaces are (100) crystallographic surfaces.

7. The method of claim 1 wherein the gate dielectric comprises a high permittivity material.

8. The method of claim 7 wherein the high permittivity material is selected from the group consisting of lanthanum oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, and combinations thereof.

9. The method of claim 7 wherein the high permittivity material has a relative permittivity greater than 5.

10. The method of claim 1 wherein the angle α

has a magnitude that is about equal to the magnitude of angle β

.

11. The method of claim 1 further comprising an annealing process to activate the implanted dopant ions.

12. The method of claim 1 wherein the semiconductor fins are oriented in the same direction.

13. The method of claim 1 wherein each gate electrode has a gate length smaller than 30 nm and each semiconductor fin is oriented in the same direction.

14. The method of claim 1 wherein each semiconductor fin comprises an etchant mask overlying the semiconductor fin.

15. The method of claim 1 wherein the insulator layer is recessed, resulting in a notch at a base of each of the semiconductor fins.

16. The method of claim 1 wherein a ratio of the doping concentration in a top surface region of the semiconductor fin to the doping concentration in the first sidewall surface of the semiconductor fin is between about 1 and about 4.

17. The method of claim 1 wherein the first and second sidewall surfaces are doped to a doping concentration of more than 1×

10²⁰ cm<sup>−

3</sup>.

18. The method of claim 1 wherein the insulator layer has a thickness of between about 100 angstroms and about 2000 angstroms.

19. The method of claim 1 wherein the gate electrode comprises poly-crystalline silicon.

20. The method of claim 1 wherein the gate electrode comprises a metal.

21. The method of claim 1, wherein the angle α

is measured in a direction opposite to the angle β

with respect to the normal of the top surface.

22. A method of forming a semiconductor-on-insulator chip, the method comprising:

providing a substrate with an insulator layer formed thereon; and

forming a plurality of multiple-gate transistors on the insulator layer, wherein at least some of the multiple-gate transistors are formed by;

forming a semiconductor fin having an orientation in a first direction;

forming a gate electrode formed adjacent a channel region portion of the semiconductor fin, the gate electrode having a gate length of less than about 30 nm; and

forming a source region and a drain region within the semiconductor fin such that the channel region is disposed between the source region and the drain region, the channel extending along a first sidewall surface of the fin, across a top surface of the fin and along a second sidewall surface of the fin, wherein the channel region is doped to a first conductivity type and the source and drain regions are doped to a second conductivity type that is different than the first conductivity type, wherein the source and drain regions are each doped by implanting ions in the first sidewall at a first angle between 26 degrees and about 63 degrees with respect to the normal of a top surface of the insulator layer and in a first plane perpendicular to the first sidewall surface and by implanting ions in the second sidewall at a second angle between 26 degrees and about 63 degrees with respect to the normal of the top surface of the insulator layer and in a second plane perpendicular to the second sidewall surface, the normal of the top surface of the insulator layer being in the first plane and the second plane, wherein the first angle is measured in a direction opposite to the second angle with respect to the normal of the top surface of the insulator layer.

23. The method of claim 22 wherein the semiconductor fin is comprised of silicon, and wherein the orientation of the semiconductor fin is in a [110] direction.

24. The method of claim 22 wherein the semiconductor fin is comprised of silicon, and wherein the orientation of the semiconductor fin is in a [100] direction.

25. A method of doping semiconductor fins of multiple-gate transistors, the method comprising:

providing a semiconductor structure comprising of a plurality of semiconductor fins overlying an insulator layer, each fin having a gate dielectric overlying a portion of that semiconductor fin, and a gate electrode overlying said gate dielectric, each of the semiconductor fins having a top surface, a first sidewall surface, and a second sidewall surface, the gate dielectric being along at least a portion of the first sidewall surface and a portion of the second sidewall surface, each of the semiconductor fins having a channel region of a first conductivity type disposed under the gate electrode, wherein the insulator layer is recessed resulting in a notch at a base of each of the semiconductor fins; and

forming a source region and/or a drain region comprising;

implanting dopant ions of a second conductivity type in a first portion of the semiconductor fins at a first angle α

to dope the first portion of the semiconductor fins, the first angle α

having a magnitude between 26 degrees and 63 degrees with respect to the normal of the top surface and being in a first plane perpendicular to the first sidewall surface, the first plane extending along the normal of the top surface; and

implanting dopant ions of the second conductivity type in a second portion of the semiconductor fins at a second angle β

to dope the second portion of the semiconductor fins, the second angle β

having a magnitude between 26 degrees and 63 degrees with respect to the normal of the top surface and being in a second plane perpendicular to the second sidewall surface, the second plane extending along the normal of the top surface, wherein the first conductivity is opposite to the second conductivity type, and wherein the first angle α

is measured in a direction opposite to the second angle β

with respect to the normal of the top surface of each of the semiconductor fins.

26. The method of claim 25 wherein implanting dopant ions at the first angle α

comprises doping the first sidewall surface and the top surface of the semiconductor fins and wherein implanting dopant ions at the second angle β

comprises doping the second sidewall surface and the top surface of the semiconductor fins.

27. The method of claim 25 wherein the channel region is located in a portion of the top surface, the first and the second sidewall surfaces of the semiconductor fin.