Method of fabricating a super junction transistor

• US 8,790,971 B1
• Filed: 03/18/2014
• Issued: 07/29/2014
• Est. Priority Date: 05/19/2011
• Status: Expired due to Fees

• Current Assignee: Anpec Electronics Corporation
• Original Assignee: Anpec Electronics Corporation
• Inventors: Lin, Yung-Fa, Hsu, Shou-Yi, Wu, Meng-Wei, Chang, Chia-Hao
• Primary Examiner(s): Tran, Thanh Y
• Application Number:
  US14/217,501
• Publication Number:
  US 20140199816A1
• Time in Patent Office: 133 Days
• Field of Search: 257/329, 257/330, 257/331, 257/332, 257/341, 257/288, 257/401, 257/335, 257/900, 257/901, 438/137, 438/192, 438/212, 438/259, 438/270, 438/271, 438/589, 438/587, 438/588, 438/197, 438/284, 438/286
• US Class Current: 438/197
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/2256 through the applied layer
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A method of fabricating a super junction transistor is provided. A drain substrate is provided. An epitaxial layer is formed on the drain substrate. A plurality of trenches is formed in the epitaxial layer. A buffer layer is formed and is in direct contact with the interior surface of the trenches. A dopant source layer is filled into the trenches. An etching process is performed to form a plurality of recessed structures above the respective trenches. A gate oxide layer is formed on the surface of each recessed trench and the dopants inside the dopant source layer are diffused into the epitaxial layer through the buffer layer to thereby form at least a body diffusion layer of the first conductivity type. A gate conductor is filled into the recessed structures to form a plurality of gate structure units. A doped source region having the first conductivity type is formed.

Claims

1. A method of fabrication of a super junction transistor, comprising:

providing a drain substrate having a first conductivity type;

forming an epitaxial layer on the drain substrate, wherein the epitaxial layer has a second conductivity type;

forming a plurality of trenches in the epitaxial layer;

forming a buffer layer in direct contact with inner surface of the trenches;

filling a dopant source layer into the trenches, wherein the dopant source layer at least has dopants with the first conductivity type;

performing an etching process to form a plurality of recessed structures above the respective trenches;

forming a gate oxide layer on the surface of the recessed trenches and concurrently diffusing the dopants inside the dopant source layer into the epitaxial layer through the buffer layer to thereby form at least a body diffusion layer with the first conductivity type;

filling a gate conductor into the recessed structures to form a plurality of gate structure units; and

forming a doped source region having the first conductivity type, wherein the doped source region is disposed in the epitaxial layer and is adjacent to each of the gate structure units.

2. The method according to claim 1, further comprising:

before performing the etching process, performing an epitaxial growth process to form a second epitaxial layer having the second conductivity type above the epitaxial layer.

3. The method according to claim 2, wherein a layout of the gate structure units is different from a layout of the body diffusion region.

4. The method according to claim 1, wherein the gate structure units are arranged in a stripe layout and the sides of the gate structure units are disposed parallel to each other.

5. The method according to claim 1, wherein the gate structure units are arranged in a matrix or an alternated layout, and a top-view shape of each gate structure unit comprises circles, squares, hexagons or polygons.