Semiconductor device and fabrication method for the same

• US 8,791,002 B2
• Filed: 09/03/2012
• Issued: 07/29/2014
• Est. Priority Date: 11/21/2011
• Status: Expired due to Fees

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Kudou, Chiaki
• Primary Examiner(s): Lee, Calvin
• Application Number:
  US13/820,445
• Publication Number:
  US 20130175548A1
• Time in Patent Office: 694 Days
• Field of Search: 438/259, 438/270, 438/579, 438/589, 257E29134-E29161, 257/283, 257/333
• US Class Current: 438/589
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A fabrication method for a semiconductor device includes the step of forming a gate insulating film on the side of a trench, the bottom thereof, and the periphery thereof. The step of forming a gate insulating film includes a step of forming a first insulating film on the side of the trench and a step of forming a second insulating film on the bottom and periphery of the trench using a high-density plasma chemical vapor deposition method. The thickness of the portions of the gate insulating film formed on the bottom and periphery of the trench is made larger than that of the portion of the gate insulating film formed on the side of the trench.

Claims

1. A fabrication method for a semiconductor device, comprising the steps of:

preparing a substrate having a semiconductor layer provided on a principal surface;

forming a trench in the semiconductor layer;

forming a gate insulating film on a side of the trench, a bottom of the trench, and a periphery of the trench; and

forming a conductive film on the gate insulating film to fill the trench and extend on the periphery of the trench, wherein

the step of forming a gate insulating film includes a step of forming a first insulating film on the side of the trench and a step of forming a second insulating film on the bottom of the trench and the periphery of the trench using a high-density plasma chemical vapor deposition method, the thickness of portions of the gate insulating film formed on the bottom of the trench and the periphery of the trench being made larger than a thickness of a portion of the gate insulating film formed on the side of the trench,

in the step of forming a conductive film, the conductive film is formed to be in contact with a portion of the first insulating film formed on the side of the trench,

in the step of preparing a substrate, the semiconductor layer is formed to include a drift region of a first conductivity type and a body region of a second conductivity type provided on the drift region,

in the step of forming a trench, the trench is formed so that the bottom of the trench is located below an interface between the drift region and the body region and above a bottom of the drift region, and

in the step of forming a gate insulating film, the gate insulating film is formed so that a top surface of the portion thereof formed on the bottom of the trench is located below the interface between the drift region and the body region.

2. The fabrication method for a semiconductor device of claim 1, wherein

the step of forming a first insulating film is performed after the step of forming a second insulating film.

3. The fabrication method for a semiconductor device of claim 1, wherein

the step of forming a first insulating film is performed before the step of forming a second insulating film.

4. The fabrication method for a semiconductor device of claim 1, wherein

the step of forming a trench includes a step of rounding a top end portion of the trench.

5. The fabrication method for a semiconductor device of claim 1, further comprising the step of:

wet-etching the second insulating film before the step of forming a conductive film,

wherein an etching amount of the second insulating film is 30% or less of a thickness of the second insulating film.

6. The fabrication method for a semiconductor device of claim 1, wherein

the semiconductor layer is made of a wide band-gap semiconductor.

7. The fabrication method for a semiconductor device of claim 6, wherein

the wide band-gap semiconductor is silicon carbide.

8. The fabrication method for a semiconductor device of claim 7, wherein

the substrate is a silicon carbide substrate, and the principal surface is a silicon plane.

9. A semiconductor device comprising:

a substrate;

a semiconductor layer provided on a principal surface of the substrate;

a trench provided in the semiconductor layer;

a gate insulating film provided on a side of the trench, a bottom of the trench, and a periphery of the trench; and

a conductive film provided on the gate insulating film to fill the trench and extend on the periphery of the trench, wherein;

the gate insulating film has a first insulating film provided on the side of the trench and a second insulating film provided on the bottom of the trench and the periphery of the trench,

a thickness of portions of the gate insulating film provided on the bottom of the trench and the periphery of the trench is larger than a thickness of a portion of the gate insulating film provided on the side of the trench, a portion of the second insulating film provided on the periphery of the trench has an inclined portion that becomes gradually thicker from the trench-side end, and the inclination angle of the inclined portion with respect to the principal surface of the substrate is 45±

5 degrees,

the conductive film is in contact with a portion of the first insulating film formed on the side of the trench,

the semiconductor layer includes a drift region of a first conductivity type and a body region of a second conductivity type provided on the drift region,

the bottom of the trench is located below an interface between the drift region and the body region and above a bottom of the drift region, and

a top surface of the portion of the gate insulating film formed on the bottom of the trench is located below the interface between the drift region and the body region.

10. The semiconductor device of claim 9, wherein

the thickness of the portion of the gate insulating film provided on the periphery of the trench is larger than that of the portion of the gate insulating film provided on the bottom of the trench.

11. The semiconductor device of claim 9, wherein

the semiconductor layer is made of a wide band-gap semiconductor.

12. The semiconductor device of claim 11, wherein

the wide band-gap semiconductor is silicon carbide.

13. The semiconductor device of claim 12, wherein

the substrate is a silicon carbide substrate, and the principal surface is a silicon surface.

14. The semiconductor device of claim 9, wherein

the first insulating film is formed on the side of the trench and the bottom and periphery of the trench.

15. The semiconductor device of claim 14, wherein

a position of the trench-side end of the portion of the second insulating film provided on the periphery of the trench corresponds with a position of a portion of the first insulating film corresponding to a top edge of the trench.

16. The semiconductor device of claim 14, wherein

a space between the trench-side end of the portion of the second insulating film provided on the periphery of the trench and a portion of the first insulating film corresponding to a top edge of the trench is 30% or less of a thickness of the portion of the second insulating film provided on the periphery of the trench.

17. The semiconductor device of claim 14, wherein

a top end portion of the trench is rounded, and

an angle of a tangent at a portion of the top end portion of the trench that is in contact with the trench-side end of the second insulating film with respect to a principal surface of the substrate is the same as the inclination angle of the inclined portion.

18. The semiconductor device of claim 14, wherein

a top end portion of the trench is rounded, and

an angle of a tangent at a portion of the top end portion of the trench that is in contact with the trench-side end of the second insulating film with respect to a principal surface of the substrate is smaller than the inclination angle of the inclined portion.