Through-silicon via structure formation process

• US 8,791,011 B2
• Filed: 02/25/2013
• Issued: 07/29/2014
• Est. Priority Date: 11/09/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Yung-Chi, Wu, Weng-Jin, Shue, Shau-Lin
• Primary Examiner(s): Quach, Tuan N.
• Application Number:
  US13/775,983
• Publication Number:
  US 20130171772A1
• Time in Patent Office: 519 Days
• Field of Search: 438/627, 438/629, 438/637, 438/648, 438/667, 438/107, 438/613, 438/653, 257/E21.584, 257/E21.585, 257/E21.586, 257/E21.597
• US Class Current: 438/627
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76871 Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

In a process, an opening is formed to extend from a front surface of a semiconductor substrate through a part of the semiconductor substrate. A metal seed layer is formed on a sidewall of the opening. A block layer is formed on only a portion of the metal seed layer. A metal layer is formed on the block layer and the metal seed layer to fill the opening.

Claims

1. A process, comprising:

forming an inter-layer dielectric (ILD) layer over a front surface of a semiconductor substrate;

forming an opening through the ILD layer and further extending from the front surface of the semiconductor substrate through a part of the semiconductor substrate;

forming a metal seed layer having a sidewall portion and a top portion, the sidewall portion on a sidewall of the opening, the top portion over the ILD layer;

forming a block layer on only a portion of the metal seed layer; and

forming a metal layer on the block layer and the metal seed layer to fill the opening,

wherein the block layer is sandwiched between the metal layer and the metal seed layer on the sidewall of the opening;

removing the top portion of the metal seed layer; and

forming an inter-metal dielectric (IMD) layer in direct contact with the ILD layer and the metal layer.

2. The process of claim 1, wherein the metal seed layer comprises a bottom portion adjacent to a back surface of the semiconductor substrate, and the bottom portion of the metal seed layer is free of the block layer.

3. The process of claim 1, wherein the metal layer comprises copper, and the metal seed layer comprises copper.

4. The process of claim 1, further comprising:

forming a barrier layer on the sidewall of the opening before said forming the metal seed layer, the barrier layer comprising at least one of TaN, Ta, TiN, or Ti.

5. The process of claim 4, further comprising:

forming a passivation layer on the sidewall of the opening before said forming the barrier layer.

6. The process of claim 5, wherein the passivation layer comprises silicon oxide.

7. The process of claim 1, further comprising:

thinning a back surface of the semiconductor substrate to expose an end of the metal layer filled the opening.

8. The process of claim 7, further comprising:

stacking a semiconductor component on the back surface of the semiconductor substrate and electrically connected to the exposed end of the metal layer.

9. The process of claim 1, wherein the block layer comprises at least one of magnesium (Mg), iron (Fe), cobalt (Co), nickel (Ni), titanium (Ti), chromium (Cr), tantalum (Ta), tungsten (W), or cadmium (Cd).

10. The process of claim 1, further comprising, before said forming the opening:

forming a contact plug in the ILD layer and electrically connected to an integrated circuit (IC) component of the semiconductor substrate.

11. The process of claim 1, wherein the forming the block layer comprises:

performing an electroplating process in which the front surface of the semiconductor substrate is positioned facing down in an electroplating bath to trapping air at a bottom of the opening.

12. The process of claim 1, wherein the forming the block layer comprises:

performing an electroplating process with no additive in an electroplating bath to make a field deposition rate higher than a bottom deposition rate.

13. The process of claim 1, wherein the forming the block layer comprises:

performing a physical vapor deposition (PVD) process using a plasma oriented obliquely to an axial direction of the opening.

14. A process, comprising:

forming an inter-layer dielectric (ILD) layer over a front surface of a semiconductor substrate;

forming an opening through the ILD layer and further extending from the front surface of the semiconductor substrate through a part of the semiconductor substrate;

forming a metal seed layer having as sidewall portion and a top portion, the sidewall portion on a sidewall of the opening, the top portion over the ILD layer;

forming a block layer on the metal seed layer on the sidewall of the opening, wherein a bottom of the opening is entirely free of the block layer;

plating a metal layer on the block layer and the metal seed layer to fill the opening;

wherein the block layer comprises at least one of magnesium (Mg), iron (Fe), cobalt (Co), nickel (Ni), titanium (Ti), chromium (Cr), tantalum (Ta), tungsten (W), or cadmium (Cd);

removing the top portion of the metal seed layer; and

forming an inter-metal dielectric (IMD) layer in direct contact with the ILD layer and the metal layer.

15. The process of claim 14, further comprising, before said forming the opening:

forming a contact plug in the ILD layer and electrically connected to an integrated circuit (IC) component of the semiconductor substrate.

16. The process of claim 15, further comprising:

thinning a back surface of the semiconductor substrate to expose an end of the metal layer filled the opening;

forming a backside dielectric layer over the thinned back surface of the semiconductor substrate; and

forming an external contact on the backside dielectric layer.

17. The process of claim 16, wherein the external contact comprises solder bumps, copper-containing bumps or combinations thereof.

18. A process, comprising:

providing a semiconductor substrate having a front surface and a back surface;

forming an inter-layer dielectric (ILD) layer over a front surface of a semiconductor substrate;

forming an opening through the ILD layer and further extending from the front surface of the semiconductor substrate through at least a part of the semiconductor substrate, wherein the opening has an aspect ratio greater than 5;

forming a metal seed layer in the opening, wherein the metal seed layer comprises a sidewall portion adjacent to the sidewall of the opening, a top portion over the ILD layer and a bottom portion adjacent to the bottom of the opening;

forming a block layer on at least a part of the sidewall portion of the metal seed layer; and

plating a metal layer on the block layer and the metal seed layer to fill the opening;

wherein the block layer comprises at least one of magnesium (Mg), iron (Fe), cobalt (Co), nickel (Ni), titanium (Ti), chromium (Cr), tantalum (Ta), tungsten (W), or cadmium (Cd); and

wherein the block layer is sandwiched between the metal layer and the sidewall portion of the metal seed layer;

removing the top portion of the metal seed layer; and

forming an inter-metal dielectric (IMD) layer in direct contact with the ILD layer and the metal layer.

19. The process of claim 18, wherein the block layer is not formed on the entire bottom portion of the metal seed layer.

20. The process of claim 18, wherein each of the metal seed layer and the metal layer comprises copper.

21. The process of claim 18, further comprising:

forming a barrier layer lining the opening before forming the metal seed layer.

22. The process of claim 21, further comprising:

forming a passivation layer lining the opening before forming the barrier layer.

23. The process of claim 18, further comprising:

performing a thinning process on the back surface of the semiconductor substrate to expose the metal layer.