Semiconductor device

• US 8,791,458 B2
• Filed: 11/21/2013
• Issued: 07/29/2014
• Est. Priority Date: 09/24/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Shishido, Hideaki
• Primary Examiner(s): ARORA, AJAY
• Application Number:
  US14/085,958
• Publication Number:
  US 20140078440A1
• Time in Patent Office: 250 Days
• US Class Current: 257/43
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: G02F 1/133388 with constructional differences between the display region and the peripheral region
• CPC Class Codes: G02F 1/133622 Colour sequential illumination
• CPC Class Codes: G02F 1/133707 Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: G02F 2202/16 conductive
• CPC Class Codes: G02F 2202/36 Micro- or nanomaterials
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device
• CPC Class Codes: H01L 29/7869 : having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Disclosed is a semiconductor device which consumes low power and has high reliability and tolerance for electrostatic discharge. The semiconductor device includes, over a first substrate, a pixel portion and a driver circuit portion both of which have a thin film transistor having an oxide semiconductor layer. The semiconductor device further possesses a second substrate to which a first counter electrode layer and a second counter electrode layer are provided, and a liquid crystal layer is interposed between the first and second substrates. The first and second counter electrode layers are provided over the pixel portion and the driver circuit portion, respectively, and the second counter electrode layer has the same potential as the first counter electrode layer.

Claims

1. A semiconductor device comprising:

a substrate;

a driver circuit portion over the substrate, the driver circuit portion including a driver circuit transistor;

a pixel portion over the substrate, the pixel portion including a pixel transistor;

a first counter electrode layer over the pixel portion with a liquid crystal layer interposed between the pixel portion and the first counter electrode layer; and

a second counter electrode layer over the driver circuit portion with the liquid crystal layer interposed between the driver circuit portion and the second counter electrode layer,

wherein the second counter electrode layer includes a branching comb-like shape, and

wherein the second counter electrode layer overlaps with the driver circuit transistor.

2. The semiconductor device according to claim 1,

wherein the pixel transistor and the driver circuit transistor further each include:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

a semiconductor layer over the gate insulating layer; and

a source electrode layer and a drain electrode layer over the semiconductor layer.

3. The semiconductor device according to claim 1,

wherein the pixel transistor and the driver circuit transistor further each include:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

a semiconductor layer over the gate insulating layer;

an insulating layer over and in contact with the semiconductor layer; and

a source electrode layer and a drain electrode layer over the semiconductor layer and the insulating layer, wherein the source electrode layer and the drain electrode layer are in contact with the semiconductor layer and the insulating layer.

4. The semiconductor device according to claim 1,

wherein the pixel transistor and the driver circuit transistor further each include:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

a source electrode layer and a drain electrode layer over the gate insulating layer; and

a semiconductor layer over and in contact with the gate insulating layer, the source electrode layer, and the drain electrode layer.

5. The semiconductor device according to claim 1,

wherein the first counter electrode layer and the second counter electrode layer are electrically connected to each other.

6. The semiconductor device according to claim 1, wherein the second counter electrode layer is at the same potential as the first counter electrode layer.

7. The semiconductor device according to claim 1, wherein the pixel transistor and the driver circuit transistor each include an oxide semiconductor layer as a channel formation region.

8. The semiconductor device according to claim 7,

wherein the oxide semiconductor layer comprises a metal oxide represented by a formula of InMO₃(ZnO)_m, where M is a metal element selected from Ga, Fe, Ni, Mn, and Co and m is larger than 0.

9. The semiconductor device according to claim 1, wherein the pixel transistor and the driver circuit transistor further comprise a planarization insulating layer thereover.

10. The semiconductor device according to claim 1,

wherein the driver circuit portion further comprises a conductive layer which overlaps with the driver circuit transistor, and

wherein the second counter electrode layer overlaps with the conductive layer.

11. The semiconductor device according to claim 10,

wherein the pixel portion further comprises a pixel electrode layer, and

wherein the conductive layer and the pixel electrode layer are transparent.

12. A semiconductor device comprising:

a first substrate;

a driver circuit portion over the first substrate, the driver circuit portion including a driver circuit transistor;

a pixel portion over the first substrate, the pixel portion including a pixel transistor;

a liquid crystal layer over the pixel portion and the driver circuit portion; and

a first counter electrode layer and a second counter electrode layer over the liquid crystal layer,

wherein the first counter electrode layer overlaps with the pixel portion,

wherein the second counter electrode layer overlaps with the driver circuit portion,

wherein the second counter electrode layer includes a branching comb-like shape, and

wherein the second counter electrode layer overlaps with the driver circuit transistor.

13. The semiconductor device according to claim 12, further comprising a second substrate over the first counter electrode layer and the second counter electrode layer.

14. The semiconductor device according to claim 12, wherein the pixel transistor and the driver circuit transistor each include an oxide semiconductor layer as a channel formation region.

15. The semiconductor device according to claim 14,

wherein the oxide semiconductor layer comprises a metal oxide represented by a formula of InMO₃(ZnO)_m, where M is a metal element selected from Ga, Fe, Ni, Mn, and Co and m is larger than 0.

16. The semiconductor device according to claim 12, further comprising a planarization insulating layer over the pixel transistor and the driver circuit transistor.

17. The semiconductor device according to claim 12,

wherein the driver circuit portion further comprises a conductive layer which overlaps with the driver circuit transistor,

wherein the second counter electrode layer overlaps with the conductive layer.

18. The semiconductor device according to claim 17,

wherein the pixel portion further comprises a pixel electrode layer, and

wherein the conductive layer and the pixel electrode layer are transparent.