Array substrate, manufacturing method of the same, and fabricating method of display device including the array substrate

• US 8,791,459 B2
• Filed: 12/17/2012
• Issued: 07/29/2014
• Est. Priority Date: 07/18/2012
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Lee, Kyu-Hwang, Moon, Tae-Hyoung, Lee, Kyung-Ha
• Primary Examiner(s): Blum, David S
• Application Number:
  US13/717,006
• Publication Number:
  US 20140021475A1
• Time in Patent Office: 589 Days
• Field of Search: 257/43, 257/59, 257/E21.704, 257/E29.296, 438/34, 438/151
• US Class Current: 257/59
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785

Abstract

An array substrate for a display device includes an insulation substrate, a gate line formed on the insulation substrate, a data line crossing the gate line to define a pixel area, a thin film transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode, a passivation layer covering the gate line, the data line and the thin film transistor and including a drain contact hole to expose the drain electrode, and a pixel electrode formed on the pixel area and being connected to the drain contact hole through the drain contact hole. Each of the data line, the source electrode and the drain electrode includes a lower layer having copper and an upper layer covering upper and side surfaces of the lower layer, and the upper layer is thinner than the lower layer.

Claims

1. An array substrate for a display device, comprising:

a substrate;

a gate pad, a gate electrode, and a gate line formed on the substrate;

a gate insulation layer formed over the gate pad, the gate electrode, and the gate line;

a semiconductor layer formed on the gate insulation layer;

a drain electrode and a source electrode formed on the semiconductor layer, a thin film transistor including the gate electrode, the drain electrode, and the source electrode;

a data line formed on the gate insulation layer and crossing the gate line to define a pixel area, the data line coupled to the source electrode;

a passivation layer formed over the data line, the source electrode, the drain electrode, and a portion of the gate insulation layer, the passivation layer including a drain contact hole to expose the drain electrode; and

a pixel electrode formed on the passivation layer in the pixel area and connected to the drain electrode through the drain contact hole, and

wherein each of the data line, the source electrode, and the drain electrode includes a lower layer having copper and an upper layer covering upper and side surfaces of the lower layer, and wherein the upper layer is thinner than the lower layer.

2. The array substrate of claim 1, wherein the gate pad is positioned at one end of the gate line and the data pad is positioned at one end of the data line, and wherein the passivation layer further includes a data pad contact hole to expose the data pad and a gate pad contact hole to expose the gate pad through the gate insulation layer and the passivation layer.

3. The array substrate of claim 1, wherein a thickness of the upper layer is in a range from 300 Å

to 900 Å

.

4. The array substrate of claim 1, wherein the semiconductor layer is an oxidation semiconductor layer and the thin film transistor includes an etch stopper formed on the oxidation semiconductor layer between the gate electrode, the source electrode, and the drain electrode.

5. The array substrate of claim 1, wherein each of the gate line and the gate electrode includes a lower layer made of copper and an upper layer that covers upper and side surfaces of the lower layer and is thinner than the lower layer.

6. The array substrate of claim 5, wherein the upper layer of each of the data line, the source electrode, and the drain electrode includes nickel and the upper layer of each of the gate line and the gate electrode includes nickel.

7. A method of fabricating an array substrate for a display device, the method comprising the steps of:

forming a gate pad, a gate electrode, and a gate line on a substrate;

forming a gate insulation layer over the gate pad, the gate electrode, and the gate line;

forming a semiconductor layer on the gate insulation layer;

forming a drain electrode and a source electrode on the semiconductor layer, a thin film transistor including the gate electrode, the drain electrode, and the source electrode;

forming a data line on the gate insulation layer, the data line crossing the gate line to define a pixel area and the data line coupled to the source electrode;

forming a passivation layer over the data line, the source electrode, the drain electrode, and a portion of the gate insulation layer, the passivation layer including a drain contact hole to expose the drain electrode; and

forming a pixel electrode on the passivation layer in the pixel area, the pixel electrode connected to the drain electrode through the drain contact hole, and

wherein each of the data line, the source electrode, and the drain electrode is formed to include a lower layer having copper and an upper layer covering upper and side surfaces of the lower layer, and wherein the upper layer is formed thinner than the lower layer.

8. The method of claim 7, wherein the gate pad is formed at one end of the gate line and a data pad is formed at one end of the data line, and wherein forming the passivation layer includes forming a data pad contact hole to expose the data pad and forming a gate pad contact hole to expose the gate pad.

9. The method of claim 7, wherein a thickness of the upper layer is in a range from 300 Å

to 900 Å

.

10. The method of claim 7, further comprising forming an etch stopper on a portion of the semiconductor layer and wherein the semiconductor layer includes oxidation semiconductor material.

11. The method of claim 7, wherein forming the gate line and the gate electrode includes forming a lower layer made of copper and forming an upper layer using a plating method, the upper layer covering upper and side surfaces of the lower layer and being thinner than the lower layer.

12. The method of claim 11, wherein the upper layer of each of the data line, the source electrode, and the drain electrode includes nickel and the upper layer of each of the gate line and the gate electrode includes nickel.

13. An array substrate for a display device, comprising:

a substrate;

a gate pad, a gate electrode, and a gate line formed on the substrate;

a gate insulation layer formed over the gate pad, the gate electrode, and the gate line;

a semiconductor layer formed on the gate insulation layer;

a drain electrode and a source electrode formed on the semiconductor layer, a thin film transistor including the gate electrode, the drain electrode, and the source electrode, the source electrode including a first source electrode layer made of a first material and a second source electrode layer made of a second material that covers the first source electrode layer, and the drain electrode including a first drain electrode layer made of the first material and a second drain electrode layer made of the second material that covers the first drain electrode layer;

a data line formed on the gate insulation layer and crossing the gate line to define a pixel area, the data line coupled to the source electrode and including a first data line layer made of the first material and a second data line layer made of the second material that covers the first data line layer;

a passivation layer formed over the data line, the source electrode, the drain electrode, and a portion of the gate insulation layer, the passivation layer including a drain contact hole to expose the drain electrode; and

a pixel electrode formed on the passivation layer in the pixel area and connected to the drain electrode through the drain contact hole, and

wherein the second data line layer is thinner than the first data line layer, the second source electrode layer is thinner than the first source electrode layer, and the second drain electrode layer is thinner than the first drain electrode layer.

14. The array substrate of claim 13, wherein the first material includes copper and the second material includes nickel.

15. The array substrate of claim 13, wherein the gate pad is positioned at one end of the gate line and the data pad is positioned at one end of the data line;

and

wherein the passivation layer further includes a data pad contact hole to expose the data pad and a gate pad contact hole to expose the gate pad through the gate insulation layer and the passivation layer.

16. The array substrate of claim 13, wherein a thickness of the second data line layer, a thickness of the second source electrode layer, and a thickness of the second drain electrode layer is each in a range of 300 Å

to 900 Å and

wherein a thickness of the first data line layer, a thickness of the first source electrode layer, and a thickness of the first drain electrode layer is each in a range of 2000 Å

to 3μ

m.

17. The array substrate of claim 13, wherein the semiconductor layer is an oxidation semiconductor layer and the thin film transistor includes an etch stopper formed on the oxidation semiconductor layer between the gate electrode, the source electrode, and the drain electrode.

18. The array substrate of claim 13, wherein the gate line includes a first gate line layer made of the first material and a second gate line layer made of the second material that covers the first gate line layer, and wherein the gate electrode includes a first gate electrode layer made of the first material and a second gate electrode layer made of the second material that covers the first gate electrode layer.

19. A method of fabricating an array substrate for a display device, the method comprising:

forming a gate pad, a gate electrode, and a gate line formed on a substrate;

forming a gate insulation layer over the gate pad, the gate electrode, and the gate line;

forming a semiconductor layer on the gate insulation layer;

forming a drain electrode and a source electrode on the semiconductor layer, a thin film transistor including the gate electrode, the drain electrode, and the source electrode, the source electrode formed to include a first source electrode layer made of a first material and a second source electrode layer made of a second material that covers the first source electrode layer, and the drain electrode formed to include a first drain electrode layer made of the first material and a second drain electrode layer made of the second material that covers the first drain electrode layer;

forming a data line on the gate insulation layer, the data line crossing the gate line to define a pixel area, the data line coupled to the source electrode and formed to include a first data line layer made of the first material and a second data line layer made of the second material that covers the first data line layer;

forming a passivation layer over the data line, the source electrode, the drain electrode, and a portion of the gate insulation layer, the passivation layer formed to include a drain contact hole to expose the drain electrode; and

forming a pixel electrode on the passivation layer in the pixel area, the pixel electrode being connected to the drain electrode through the drain contact hole, and

wherein the second data line layer is thinner than the first data line layer, the second source electrode layer is thinner than the first source electrode layer, and the second drain electrode layer is thinner than the first drain electrode layer.

20. The method of claim 19, wherein the first material includes copper and the second material includes nickel.