Thin-film transistor substrate

• US 8,791,463 B2
• Filed: 04/07/2011
• Issued: 07/29/2014
• Est. Priority Date: 04/21/2010
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Misaki, Katsunori
• Primary Examiner(s): Lee, Cheung
• Assistant Examiner(s): JOY, JEREMY J
• Application Number:
  US13/578,738
• Publication Number:
  US 20120305925A1
• Time in Patent Office: 1,209 Days
• Field of Search: 257/59, 257/72, 438/34
• US Class Current: 257/72
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Gate electrodes, a gate insulating layer, and an oxide semiconductor layer are simultaneously formed to form a multilayer structure, so that an SOG film serves as an etching stopper on channel regions in forming source electrodes and drain electrodes. In the SOG film, channel isolation holes are formed in positions each of which is located between adjacent two of TFTs connected to a common one of the gate lines, and corresponds to the common gate line. The oxide semiconductor layer of the adjacent TFTs is divided in each channel isolation hole. Terminal sections of the gate lines are exposed in the terminal section exposing holes formed in positions each corresponding to a gate line end portion. The pixel electrode is made of a film identical to a film forming one layer included in the drain electrode.

Claims

1. A thin film transistor substrate comprising:

a base substrate;

a plurality of gate lines extending parallel to each other on the base substrate;

a plurality of source lines extending parallel to each other in a direction intersecting the gate lines;

thin film transistors each of which is provided at an associated one of intersections of the gate lines and the source lines; and

pixel electrodes each of which is provided to an associated one of the thin film transistors, wherein

each of the thin film transistors includes a gate electrode connected to the gate line forming an associated one of the intersections, a gate insulating layer provided on the gate electrode, an oxide semiconductor layer provided on the gate insulating layer and including a channel region overlapping the gate electrode, a source electrode connected to one side of the oxide semiconductor layer and connected to the source line forming the associated one of the intersections, and a drain electrode connected to the other side of the oxide semiconductor layer such that the drain electrode faces the source electrode,

each of the thin film transistors is configured such that side end faces of the gate electrode, the gate insulating layer, and the oxide semiconductor layer are formed to be flush with one another to form a multilayer structure, a stopper insulating film is provided to cover the multilayer structure, a pair of contact holes for connection to the oxide semiconductor layer is formed in the stopper insulating film to connect the source electrode to the oxide semiconductor layer via one of the contact holes, and to connect the drain electrode to the oxide semiconductor layer via the other of the contact holes, and the stopper insulating film serves as an etching stopper on the channel region when the source electrode and the drain electrode are formed,

an insulating layer made of a film identical to a film forming the gate insulating layer is stacked also on the gate lines,

the stopper insulating film is provided to cover at least part of side end faces of the gate lines and of the insulating layer,

the stopper insulating film has channel isolation holes formed in positions each of which is located between adjacent two of the thin film transistors connected to a common one of the gate lines, and corresponds to the common gate line, where the oxide semiconductor layer of the adjacent thin film transistors is divided in each of the channel isolation holes so as to isolate the channel regions of the adjacent thin film transistors from each other,

the stopper insulating film has terminal section exposing holes formed in positions each corresponding to an end portion of the gate line, where the end portion of the gate line is exposed in each of the terminal section exposing holes from the insulating layer to form a terminal section,

each of the pixel electrodes is made of a film identical to at least one layer included in the drain electrode,

the thin film transistors are covered with a protective insulating film,

each of the drain electrodes includes a transparent conductive layer and a light shielding conductive layer which are sequentially stacked,

each of the pixel electrodes is made of a film identical to a film forming the transparent conductive layer,

in the protective insulating film, openings are formed in positions each corresponding to the pixel electrode, and

the light shielding conductive layer of each of the drain electrodes has an end face facing an associated one of the pixel electrodes, where the end face matches an inner surface of the opening in the protective insulating film.

2. The thin film transistor substrate of claim 1, wherein

each of the channel isolation holes is formed to fit within the position of the stopper insulating film corresponding to the gate line, and

the oxide semiconductor layer is formed also on the region corresponding to the gate line, and serves as an etching stopper when the channel isolation holes are formed in the stopper insulating film.

3. The thin film transistor substrate of claim 1, wherein

each of the channel isolation holes is formed in the position of the stopper insulating film corresponding to the gate line to extend across the gate line in a width direction of the gate line.

4. The thin film transistor substrate of claim 1, wherein

the stopper insulating film is made of a spin-on glass material.

5. The thin film transistor substrate of claim 1, wherein

the oxide semiconductor layer is made of indium-gallium-zinc-oxide-based metal oxide.

6. A liquid crystal display device comprising:

a thin film transistor substrate of claim 1;

a counter substrate provided to face the thin film transistor substrate; and

a liquid crystal layer provided between the thin film transistor substrate and the counter substrate.

7. A method for fabricating the thin film transistor substrate of claim 1, the method comprising:

a first patterning step of

sequentially forming a first conductive film, a first insulating film, and an oxide semiconductor film on the base substrate to form a multilayer film, and then

patterning the multilayer film by using a first photomask to form the gate lines and the gate electrodes from the first conductive film, the insulating layer from the first insulating film, and the oxide semiconductor layer from the oxide semiconductor film such that a multilayer structure including the gate lines, the gate electrodes, and the insulating layer and the oxide semiconductor layer which are sequentially stacked on the gate lines and the gate electrodes is formed, where part of the insulating layer which corresponds to the gate electrodes form the gate insulating layer;

a second patterning step of

forming a second insulating film to cover the multilayer structure, and then

patterning the second insulating film by using a second photomask to form a pair of contact holes extending to the oxide semiconductor layer in positions corresponding to each of the gate electrodes, channel isolation holes extending to the oxide semiconductor layer in positions each of which is located between adjacent two of the gate electrodes connected to a common one of the gate lines, and corresponds to the common gate line, and terminal section exposing holes in positions each corresponding to an end portion of the gate line so that the second insulating film serves as the stopper insulating film;

a third patterning step of

forming a second conductive film on the stopper insulating film, and then

by using the stopper insulating film as an etching stopper, patterning the second conductive film by using a third photomask to form the source lines, the source electrodes, the drain electrodes, and the pixel electrodes,

dividing the oxide semiconductor layer by removing part of the oxide semiconductor layer via each of the channel isolation holes so that parts of the oxide semiconductor layer which are located above the adjacent gate electrodes connected to the common gate line are isolated from each other, and

removing part of the oxide semiconductor layer via each of the terminal section exposing holes to expose the insulating layer; and

a fourth patterning step of patterning the insulating layer exposed from the stopper insulating film via the terminal section exposing holes by using a fourth photomask to expose end portions of the gate lines from the insulating layers to form terminal sections of the gate lines.