Semiconductor devices, assemblies and constructions

• US 8,791,506 B2
• Filed: 09/02/2011
• Issued: 07/29/2014
• Est. Priority Date: 08/28/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Taylor, Ted, Yang, Xiawan
• Primary Examiner(s): MITCHELL, JAMES M
• Application Number:
  US13/224,804
• Publication Number:
  US 20110316091A1
• Time in Patent Office: 1,061 Days
• Field of Search: 257/203, 257/206, 257/278
• US Class Current: 257/203
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material

Abstract

Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

Claims

1. A semiconductor construction, comprising:

a base;

an array of semiconductor material active areas supported by the base, the array comprising columns and rows of the active areas, the columns of active areas having non-parallel adjacent active areas; and

insulative material alternating with the active areas along the columns of the array;

the insulative material extending under the active areas and entirely separating individual active areas from the base.

2. The construction of claim 1 wherein the base comprises monocrystalline silicon, and wherein the active areas also comprise monocrystalline silicon.

3. The construction of claim 2 further comprising transistor gates over the active areas, and conductively-doped source/drain regions within the active areas.

4. The construction of claim 1 wherein the insulative material consists of silicon dioxide.

5. A semiconductor construction, comprising:

a monocrystalline silicon base;

an array of monocrystalline silicon islands supported by the base, the array comprising columns and rows of the islands, the islands being spaced from one another by silicon dioxide, adjacent islands in the columns of islands being non-parallel relative to each other; and

the silicon dioxide extending under the islands and entirely separating the islands from the base.

6. The construction of claim 5 further comprising transistor gates over the islands, and conductively-doped source/drain regions within the islands.

7. A semiconductor construction, comprising:

a monocrystalline silicon base;

a plurality of monocrystalline silicon islands supported by the base, the islands being spaced from one another by silicon dioxide, the plurality of islands comprising columns of adjacent islands where adjacent islands are non-parallel relative to each other;

the silicon dioxide extending under the islands and entirely separating the islands from the base;

transistor gates over the islands, with two transistor gates being associated with each island; and

source/drain regions adjacent the transistor gates.

8. A semiconductor construction, comprising:

a base, the base consisting essentially of silicon;

an array of semiconductor areas supported by the base, the array comprising columns and rows of the semiconductor areas, the columns of semiconductive areas having non-parallel adjacent semiconductive areas;

lines of first insulative material along the columns of the semiconductor areas, the lines directly contacting ends of the semiconductor areas;

the lines of first insulative material and rows of the semiconductor areas defining a lattice;

sections of second insulative material at locations between the rows and lines of the lattice, such that said sections alternate with semiconductor areas along the columns of the array; and

regions of the second insulative material under the semiconductor areas;

the regions extending from opposing sides of individual semiconductor areas to entirely separate the individual semiconductor areas from the base.

9. The construction of claim 8 further comprising transistor gates over the semiconductor areas, and conductively-doped source/drain regions within the semiconductor areas.

10. The construction of claim 8 wherein the first insulative material consists of silicon dioxide.

11. The construction of claim 8 wherein the second insulative material consists of silicon dioxide.

12. The construction of claim 8 wherein the first insulative material and the second insulative material are of a common composition relative to one another.