High density gallium nitride devices using island topology

• US 8,791,508 B2
• Filed: 04/13/2011
• Issued: 07/29/2014
• Est. Priority Date: 04/13/2010
• Status: Active Grant

• Current Assignee: GaN Systems Inc. (Infineon Technologies AG)
• Original Assignee: GaN Systems Inc. (Infineon Technologies AG)
• Inventors: Roberts, John, Mizan, Ahmad, Patterson, Girvan, Klowak, Greg
• Primary Examiner(s): Menz, Laura
• Assistant Examiner(s): Malek, Maliheh
• Application Number:
  US13/641,003
• Publication Number:
  US 20130049010A1
• Time in Patent Office: 1,203 Days
• Field of Search: 257/76, 257/192, 257194-195, 257/200, 257/206, 257/208, 257/213, 257288-289, 257/365, 257/369, 257/390, 257/E29.246, 257/E29.252, 257/E21.403, 257/E21.405, 257/E21.407, 257/E29.249, 438128-129, 438/167, 438/172, 438/587, 438/604
• US Class Current: 257/206
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/1033 : Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A Gallium Nitride (GaN) series of devices—transistors and diodes are disclosed—that have greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The devices also include a simpler and superior flip chip connection scheme and a means to reduce the thermal resistance. A simplified fabrication process is disclosed and the layout scheme which uses island electrodes rather than finger electrodes is shown to increase the active area density by two to five times that of conventional interdigitated structures. Ultra low on resistance transistors and very low loss diodes can be built using the island topology. Specifically, the present disclosure provides a means to enhance cost/effective performance of all lateral GaN structures.

Claims

1. A nitride semiconductor device comprising:

a) a substrate;

b) a nitride semiconductor layer formed on a main surface of the substrate, the nitride semiconductor layer having a channel region through which electrons drift in a direction parallel to the main surface;

c) a plurality of first island electrodes and a plurality of second island electrodes formed on the nitride semiconductor layer, spaced apart from each other and arranged alternately to produce a multiplicity of two-dimensional active regions in the nitride semiconductor layer, wherein the first and second island electrodes are, respectively, source and drain electrodes of a multi-island transistor, or, anode and cathode electrodes of a multi-island diode;

d) an insulating layer formed on the nitride semiconductor layer having a plurality of openings for connections to the first and second island electrodes and any common electrode connections areas;

e) a plurality of ball or bump connections connected through the plurality of openings to either of respective first or second island electrodes; and

wherein a plurality of through-substrate via connections are formed where the first or second island electrodes or common electrode connection areas are not connected using a ball or bump connections, a large single electrode common pad is provided on a side of the substrate opposite the main surface, and the plurality of through-substrate via connections provide connections from a top of the first or second island electrodes or from respective common electrode connection areas to the common pad.

2. The nitride semiconductor device according claim 1, wherein the first and second island electrodes have a rectangular shape.

3. The nitride semiconductor device according to claim 1, wherein the first and second island electrodes have a triangular shape.

4. The nitride semiconductor device according to claim 1, wherein the first and second island electrodes are a combination of various different polygon shapes to optimize active area usage.

8. The nitride semiconductor device according to claim 1 wherein the substrate is conductive and via connections are provided from either a top of each first island electrode or a top of each second island electrode, or from a top of each respective common connection area, to the substrate.

9. The nitride semiconductor device according to claim 1, comprising a silicide/polysilicon interconnect and contact system or a metal interconnect and contact system.

10. The nitride semiconductor device according to claim 1 wherein the first and second island electrodes are made from two metal layers of different work functions.

5. A nitride semiconductor device comprising:

a) a substrate

b) a nitride semiconductor layer formed on a main surface of the substrate, the nitride semiconductor layer having a channel region through which electrons drift in a direction parallel to the main surface;

c) a plurality of first island electrodes and a plurality of second island electrodes formed on the nitride semiconductor layer, spaced apart from each other and arranged alternately to produce a multiplicity of two-dimensional active regions in the nitride semiconductor layer, wherein the first and second island electrodes are, respectively, source and drain electrodes of a multi-island transistor, or, anode and cathode electrodes of a multi-island diode;

d) an insulating layer formed on the nitride semiconductor layer having a plurality of openings for connections to the first and second island electrodes and any common electrode connections areas; and

e) a plurality of ball or bump connections connected through the plurality of openings to the respective first and second island electrodes;

wherein

a single or a plurality of first metal layers allow for electrical connection of a plurality of first island electrodes to a common first electrode gold bump connection; and

a single or a plurality of second metal layers allow for electrical connection of a plurality of second island electrodes to a common second electrode gold bump connection.

6. The nitride semiconductor device according to claim 5, wherein the first and second metal layers provide separation of high voltage stresses between the first and second electrodes and their connections.

7. The nitride semiconductor device according to claim 5 wherein the first and second metal layers are fabricated by a lift-off resist mask process.

11. A nitride semiconductor device comprising:

a) a substrate;

b) a nitride semiconductor layer formed on a main surface of the substrate, the nitride semiconductor layer having a channel region through which electrons drift in a direction parallel to the main surface;

c) a plurality of first island electrodes and a plurality of second island electrodes formed on the nitride semiconductor layer, spaced apart from each other and arranged alternately to produce a multiplicity of two-dimensional active regions in the nitride semiconductor layer, wherein the first and second island electrodes are, respectively, anode and cathode electrodes of a multi-island diode;

d) an insulating layer formed on the nitride semiconductor layer having a plurality of openings for connections to the first and second island electrodes and any common electrode connections areas; and

e) a plurality of ball or bump connections connected through the plurality of openings to the respective first and second island electrodes; and

wherein, the plurality of first island electrodes and the plurality of second island electrodes each have a plurality of castellated peninsulas extending from at least one side, the castellated peninsulas of first island electrodes being interleaved with castellated peninsulas of adjacent second island electrodes.

12. A nitride semiconductor device comprising:

a) a substrate;

b) a nitride semiconductor layer formed on a main surface of the substrate and having a channel region through which electrons drift in a direction parallel to the main surface;

c) a plurality of first island electrodes and a plurality of second island electrodes formed on the nitride semiconductor layer, spaced apart from each other and arranged alternately to produce two dimensional active regions in the nitride semiconductor layer;

d) a plurality of third strip electrodes that are formed on the nitride semiconductor layer in regions between each first island electrode and each second island electrode and serve as gate electrodes of a multi-island field effect transistor, where each of the island electrodes is either a drain electrode or a source electrode of a field effect transistor;

e) an insulating layer formed on the nitride semiconductor layer having a plurality of openings for connections to the first, second, third electrodes and any common electrode connection areas which have been formed by electrically connecting the first and second and third electrodes; and

f) a plurality of ball or hump connections connected through the plurality of openings to the respective first and second and third electrodes and any common electrode connection areas; and

wherein;

the plurality of first island electrodes and the plurality of second island electrodes each have a plurality of castellated peninsulas extending from at least one side, the castellated peninsulas of the first island electrodes being interleaved with castellated peninsulas of adjacent second island electrodes; and

the plurality of third strip electrodes that are formed on the nitride semiconductor layer in regions between interleaved castellated peninsulas of the first and second island electrodes and serve as gate electrodes of a multi-island field effect transistor, where each of the island electrodes is either a drain electrode or a source electrode of a field effect transistor.

13. The nitride semiconductor device according to claim 12 wherein a layer of p-type GaN material or a layer of p-type AlGaN material is provided under the gate electrode to create an enhancement device.

14. The nitride semiconductor device of claim 12 wherein the nitride semiconductor layer comprises a heterolayer consisting of a layer of undoped gallium nitride (GaN) and an overlying layer undoped aluminum gallium nitride (AlGaN).