Power semiconductor device including a double metal contact

• US 8,791,525 B2
• Filed: 02/25/2008
• Issued: 07/29/2014
• Est. Priority Date: 02/25/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Montgomery, Robert, Burke, Hugo, Parsonage, Philip, Johns, Susan, Jones, David Paul
• Primary Examiner(s): Tsai, H
• Application Number:
  US12/036,718
• Publication Number:
  US 20090212435A1
• Time in Patent Office: 2,346 Days
• Field of Search: 257330-347
• US Class Current: 257/330
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/11019 for protecting parts during the process
• CPC Class Codes: H01L 2224/11466 Conformal deposition, i.e. blanket deposition of a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/11831 involving a chemical process, e.g. etching the bump connector
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/05494 : having an amorphous microstructure, i.e. glass
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.

Claims

1. A power semiconductor device comprising:

a semiconductor body including an active region on one surface thereof, said active region including source regions and gate electrodes;

a first metal layer disposed on said one surface and coupled to said source regions;

a gate bus arrangement disposed over said one surface lateral to and spaced from said first metal layer, said gate bus arrangement including a metallic gate bus disposed over a polysilicon gate bus and an insulation body between said polysilicon gate bus and said one surface, wherein said gate bus arrangement is not disposed within a trench, and said gate bus arrangement is disposed entirely above said one surface;

a buffer body disposed over said gate bus arrangement and in a space between said gate bus arrangement and said first metal layer; and

a second metal layer disposed over said first metal layer and extending over and covering said buffer body, a portion of said second metal layer forming a gate pad disposed over said active region and coupled to said metallic gate bus through said buffer body.

2. The power semiconductor device of claim 1, wherein said first metal layer and said metallic gate bus are less than 2 microns thick.

3. The power semiconductor device of claim 1, wherein said second metal layer is more then 4 microns thick.

4. The power semiconductor device of claim 1, wherein said second metal layer is more then 4-20 microns thick.

5. The power semiconductor device of claim 1, wherein said buffer body is comprised of polyimide.

6. The power semiconductor device of claim 1, further comprising a hermetic sealant body disposed between said gate bus arrangement and said buffer body.

7. The power semiconductor device of claim 6, wherein said hermetic sealant body comprises a stack of PSG and silicon nitride.

8. A trench MOSFET comprising:

source regions and gate electrodes within trenches in a semiconductor body;

a drift region and a drain region below said source regions;

a first metal layer disposed on and coupled to said source regions;

a gate bus arrangement disposed lateral to and spaced from said first metal layer, said gate bus arrangement including a metallic gate bus disposed over a polysilicon gate bus and an insulation body between said polysilicon gate bus and a top surface of said semiconductor body, wherein said gate bus arrangement is not disposed within a trench, and said gate bus arrangement is disposed entirely above said top surface;

a buffer disposed over said gate bus arrangement and in a space between said gate bus arrangement and said first metal layer;

a conductive gate pad disposed over said buffer and over an active region of said trench MOSFET, said conductive gate pad coupled to said metallic gate bus through said buffer;

a second metal layer disposed over said first metal layer and extending over and covering said buffer.

9. The trench MOSFET of claim 8, wherein said second metal layer forms said conductive gate pad.

10. The trench MOSFET of claim 8, further comprising a hermetic sealant disposed between said gate bus arrangement and said buffer.

11. The trench MOSFET of claim 10, wherein said hermetic sealant comprises PSG.

12. The trench MOSFET of claim 10, wherein said hermetic sealant comprises silicon nitride.