Semiconductor device including gate and conductor electrodes

• US 8,791,529 B2
• Filed: 04/02/2013
• Issued: 07/29/2014
• Est. Priority Date: 02/05/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko
• Primary Examiner(s): Pham, Thanh V
• Application Number:
  US13/855,203
• Publication Number:
  US 20130228776A1
• Time in Patent Office: 483 Days
• Field of Search: 257/288, 257/412, 257/E29.255, 257/E21.41, 438/149
• US Class Current: 257/412
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An object is to provide a field effect transistor (FET) having a conductor-semiconductor junction, which has excellent characteristics, which can be manufactured through an easy process, or which enables high integration. Owing to the junction between a semiconductor layer and a conductor having a work function lower than the electron affinity of the semiconductor layer, a region into which carriers are injected from the conductor is formed in the semiconductor layer. Such a region is used as an offset region of the FET or a resistor of a semiconductor circuit such as an inverter. Further, in the case of setting up such an offset region and a resistor in one semiconductor layer, an integrated semiconductor device can be manufactured.

Claims

1. A semiconductor device comprising:

a semiconductor layer comprising an offset region;

a first conductor electrode and a second conductor electrode over and in contact with one surface of the semiconductor layer; and

a gate over the semiconductor layer,

wherein the offset region is provided in at least one of a region between the first conductor electrode and the gate and a region between the second conductor electrode and the gate,

wherein the offset region of the semiconductor layer comprises an oxide semiconductor, and

wherein a carrier concentration of the oxide semiconductor is lower than or equal to 10¹²/cm³.

2. The semiconductor device according to claim 1, further comprising a third conductor electrode over and in contact with the one surface of the semiconductor layer,

wherein the gate overlaps with at least part of a region between the first conductor electrode and the second conductor electrode, and

wherein the gate does not overlap with a region between the second conductor electrode and the third conductor electrode.

3. The semiconductor device according to claim 2, wherein a width of a first portion of the semiconductor layer between the first conductor electrode and the second conductor electrode is wider than a width of a second portion of the semiconductor layer between the second conductor electrode and the third conductor electrode.

4. The semiconductor device according to claim 1, further comprising a gate insulating film between the semiconductor layer and the gate.

5. The semiconductor device according to claim 1, wherein a width of the offset region is more than or equal to 10 nm and less than or equal to 100 nm.

6. The semiconductor device according to claim 1, wherein a portion of the first conductor electrode and a portion of the second conductor electrode which are in contact with the semiconductor layer have a work function lower than a sum of an electron affinity of the semiconductor layer and 0.3 electron volts.

7. The semiconductor device according to claim 1, wherein a work function of a portion of the gate which is the closest to the semiconductor layer is higher than a sum of an electron affinity of the semiconductor layer and 0.6 electron volts.

8. The semiconductor device according to claim 1, wherein a junction between the semiconductor layer and the first conductor electrode and a junction between the semiconductor layer and the second conductor electrode are each an ohmic junction.

9. The semiconductor device according to claim 1, wherein the gate comprises a material selected from the group consisting of platinum, gold, tungsten, and indium nitride.

10. The semiconductor device according to claim 1, wherein the carrier concentration of the oxide semiconductor is derived from a donor or an acceptor.

11. The semiconductor device according to claim 1, wherein the oxide semiconductor is an i-type.

12. The semiconductor device according to claim 1, wherein the oxide semiconductor includes indium and zinc.

13. A semiconductor device comprising:

a semiconductor layer comprising an offset region;

a first conductor electrode and a second conductor electrode over and in contact with one surface of the semiconductor layer; and

a gate over the semiconductor layer,

wherein the offset region is provided in at least one of a region between the first conductor electrode and the gate and a region between the second conductor electrode and the gate,

wherein a whole region of the semiconductor layer comprises an oxide semiconductor, and

wherein a carrier concentration of the oxide semiconductor is lower than or equal to 10¹²/cm³.

14. The semiconductor device according to claim 13, further comprising a third conductor electrode over and in contact with the one surface of the semiconductor layer,

wherein the gate overlaps with at least part of a region between the first conductor electrod and the second conductor electrode, and

wherein the gate does not overlap with a region between the second conductor electrode and the third conductor electrode.

15. The semiconductor device according to claim 14, wherein a width of a first portion of the semiconductor layer between the first conductor electrode and the second conductor electrode is wider than a width of a second portion of the semiconductor layer between the second conductor electrode and the third conductor electrode.

16. The semiconductor device according to claim 13, further comprising a gate insulating film between the semiconductor layer and the gate.

17. The semiconductor device according to claim 13, wherein a width of the offset region is more than or equal to 10 nm and less than or equal to 100 nm.

18. The semiconductor device according to claim 13, wherein a portion of the first conductor electrode and a portion of the second conductor electrode which are in contact with the semiconductor layer have a work function lower than a sum of an electron affinity of the semiconductor layer and 0.3 electron volts.

19. The semiconductor device according to claim 13, wherein a work function of a portion of the gate which is the closest to the semiconductor layer is higher than a sum of an electron affinity of the semiconductor layer and 0.6 electron volts.

20. The semiconductor device according to claim 13, wherein a junction between the semiconductor layer and the first conductor electrode and a junction between the semiconductor layer and the second conductor electrode are each an ohmic junction.

21. The semiconductor device according to claim 13, wherein the gate comprises a material selected from the group consisting of platinum, gold, tungsten, and indium nitride.

22. The semiconductor device according to claim 13, wherein the carrier concentration of the oxide semiconductor is derived from a donor or an acceptor.

23. The semiconductor device according to claim 13, wherein the oxide semiconductor is an i-type.

24. The semiconductor device according to claim 13, wherein the oxide semiconductor includes indium and zinc.