Backside-illuminated image sensor having a supporting substrate

• US 8,791,541 B2
• Filed: 07/05/2012
• Issued: 07/29/2014
• Est. Priority Date: 11/06/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Kuan-Chieh, Yaung, Dun-Nian, Wu, Chih-Jen, Huang, Chen-Ming
• Primary Examiner(s): MONTALVO, EVA Y
• Application Number:
  US13/542,591
• Publication Number:
  US 20130001725A1
• Time in Patent Office: 754 Days
• Field of Search: 257/444, 257/447, 257/433, 257/432, 257/E27.133, 438/70, 438/66
• US Class Current: 257/447
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0239 Material of the redistribution layers
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 27/14618 : Containers
• CPC Class Codes: H01L 27/14621 : Colour filter arrangements
• CPC Class Codes: H01L 27/14627 : Microlenses
• CPC Class Codes: H01L 27/1464 : Back illuminated imager structures
• CPC Class Codes: H01L 27/14645 : Colour imagers
• CPC Class Codes: H01L 27/14687 : Wafer level processing
• CPC Class Codes: H01L 27/14689 : MOS based technologies
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12043 : Photo diode
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 31/0232 : Optical elements or arrangements associated with the device H01L31/0236 takes precedence; for photovoltaic cells H01L31/054; for photovoltaic modules H02S40/20
• CPC Class Codes: H01L 31/18 : Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• CPC Class Codes: H05K 2201/10151 : Sensor
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components

Abstract

Provided is a method of fabricating a backside illuminated image sensor that includes providing a device substrate having a frontside and a backside, where pixels are formed at the frontside and an interconnect structure is formed over pixels, forming a re-distribution layer (RDL) over the interconnect structure, bonding a first glass substrate to the RDL, thinning and processing the device substrate from the backside, bonding a second glass substrate to the backside, removing the first glass substrate, and reusing the first glass substrate for fabricating another backside-illuminated image sensor.

Claims

1. An image sensor comprising:

a device substrate having a frontside and a backside;

a plurality of pixels disposed at the frontside of the device substrate;

an interconnect structure disposed over the pixels;

a re-distribution layer (RDL) spaced apart from the interconnect structure;

a frontside substrate disposed between and connecting the RDL and the interconnect structure such that the RDL is spaced apart from the interconnect structure by the frontside substrate; and

a contact assembly electrically coupling the interconnect structure and the redistribution layer, wherein the contact assembly is disposed along an outer sidewall of the frontside substrate.

2. The image sensor of claim 1, wherein the frontside substrate is configured to provide support for thinning and processing the device substrate from the backside.

3. The image sensor of claim 1, wherein the interconnect structure includes a passivation layer, and wherein the frontside substrate is bonded to the passivation layer.

4. The image sensor of claim 1, further comprising a backside substrate disposed on the backside of the device substrate.

5. The image sensor of claim 1, further comprising:

a color filter layer disposed on the backside of the device substrate; and

a microlens layer disposed on the color filter layer,

wherein a cavity is formed between the backside substrate and the device substrate and

wherein the color filter layer and the microlens layer are disposed within the cavity.

6. The image sensor of claim 1, further comprising a board coupled to the RDL for chip packaging.

7. The image sensor of claim 1, wherein the frontside substrate is a glass substrate.

8. An image sensor device comprising:

a device substrate having a frontside and a backside, the frontside having a plurality of pixels formed thereupon;

an interconnect structure formed at the frontside;

a re-distribution layer (RDL) formed over the interconnect structure; and

a first substrate disposed between the interconnect structure and the RDL,

wherein the first substrate is a glass substrate, and

wherein the interconnect structure is separated from the RDL by the first substrate.

9. The image sensor of claim 8, wherein the first substrate is configured to provide support for thinning and processing the device substrate from the backside.

10. The device of claim 9, wherein the first substrate is further configured to allow electrical coupling of the interconnect structure and the RDL.

11. The device of claim 8, further comprising a contact assembly electrically coupling the interconnect structure and the redistribution layer.

12. The device of claim 8, further comprising:

a planarization layer disposed on the backside of the device substrate;

a color filter layer disposed on the planarization layer; and

a microlens layer disposed on the color filter layer.

13. The device of claim 12, further comprising:

a dam structure formed on the backside of the device substrate, the dam structure surrounding the color filter layer and the microlens layer; and

a second substrate disposed on the dam structure to form a cavity that contains the color filter layer and the microlens layer.

14. A semiconductor device comprising:

a device substrate;

a transistor formed upon the device substrate;

an interconnect structure formed over the device substrate;

a supporting substrate formed over the interconnect structure opposite the device substrate;

a re-distribution layer (RDL) formed over the supporting substrate and separated from the interconnect structure by the supporting substrate; and

a contact assembly coupling the interconnect structure to the RDL,

wherein the supporting substrate is a glass substrate.

15. The device of claim 14, wherein the supporting substrate is formed over a frontside surface of the device substrate and is configured to provide support for thinning and processing a backside surface of the device substrate.

16. The device of claim 14, further comprising a passivation layer formed between the interconnect structure and the supporting substrate, the supporting substrate bonded to the passivation layer.

17. The device of claim 16, wherein the passivation layer includes bonding pads configured to provide electrical connection with the interconnect structure.

18. The device of claim 17, wherein the RDL is isolated from the device substrate except for an electrical connection to the bonding pads.

19. The device of claim 14, wherein the transistor is part of a pixel device.