Wafer backside interconnect structure connected to TSVs

• US 8,791,549 B2
• Filed: 07/07/2010
• Issued: 07/29/2014
• Est. Priority Date: 09/22/2009
• Status: Active Grant

• Current Assignee: Advanced Manufacturing Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ming-Fa, Chiou, Wen-Chih, Shue, Shau-Lin
• Primary Examiner(s): HO, HOANG QUAN TRAN
• Application Number:
  US12/832,019
• Publication Number:
  US 20110068466A1
• Time in Patent Office: 1,483 Days
• Field of Search: None
• US Class Current: 257/621
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05546 Dual damascene structure
• CPC Class Codes: H01L 2224/05547 comprising a core and a coating
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/14181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/811 : the bump connector being supplied to the parts to be connected in the bonding apparatus
• CPC Class Codes: H01L 2224/8136 : Bonding interfaces of the semiconductor or solid state body
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.

Claims

1. An integrated circuit structure comprising:

a semiconductor substrate having an active semiconductor device formed on a first side of the semiconductor substrate;

a conductive via passing through the semiconductor substrate;

a metal feature on a second side of the semiconductor substrate opposing the first side of the semiconductor substrate, the metal feature comprising;

a metal pad overlying and contacting the conductive via, wherein from a top-down perspective, all horizontal dimensions of the metal pad are greater than respective horizontal dimensions of the conductive via; and

a metal line higher than the conductive via, relative the second side of the semiconductor substrate, wherein the metal line comprises a dual damascene structure; and

a bump overlying the metal line.

2. The integrated circuit structure of claim 1, wherein the metal pad further comprises:

a first bottom surface contacting a conductive barrier layer, wherein the conductive barrier layer contacts a top surface of the conductive via; and

a second bottom surface higher than the second side of the semiconductor substrate and lower than the first bottom surface.

3. The integrated circuit structure of claim 1, wherein the dual damascene structure is in a same dielectric layer as the metal pad.

4. The integrated circuit structure of claim 1, wherein the dual damascene structure is in a dielectric layer over the metal pad.

5. The integrated circuit structure of claim 1 further comprising a polyimide layer, wherein the metal pad is in the polyimide layer.

6. The integrated circuit structure of claim 1, wherein the metal feature further comprises a conductive barrier layer.

7. An integrated circuit structure comprising:

a semiconductor substrate having a front side and a backside, wherein the backside is opposite the front side;

an active device formed on the front side;

a through-substrate via (TSV) penetrating through the semiconductor substrate;

a first dielectric layer on the backside of the semiconductor substrate, wherein the dielectric layer comprises a metal pad overlying the TSV, wherein from a top-down perspective, all horizontal dimensions of the metal pad are greater than respective horizontal dimensions of the TSV; and

a second dielectric layer on the backside of the semiconductor substrate and over the first dielectric layer relative the backside of the semiconductor substrate, the second dielectric layer comprises a first metal line, wherein the first metal line comprises a dual-damascene structure.

8. The integrated circuit structure of claim 7, wherein the metal pad comprises a conductive barrier layer.

9. The integrated circuit structure of claim 7, wherein the first metal line further comprises a conductive barrier layer.

10. The integrated circuit structure of claim 7, wherein the second dielectric layer further comprises a second metal line, the second metal line comprising a single damascene structure.

11. The integrated circuit structure of claim 7, wherein the TSV comprises a portion penetrating into the first dielectric layer.

12. The integrated circuit structure of claim 7, further comprising an isolation layer covering at least a portion of sidewalls of the TSV.

13. The integrated circuit structure of claim 7, wherein the first dielectric layer comprises a portion between the metal pad and the semiconductor substrate.

14. The integrated circuit structure of claim 7, further comprising a bump overlying the first metal line.

15. The integrated circuit structure of claim 7, wherein the metal pad comprises:

a first bottom surface contacting a top surface of the TSV; and

a second bottom surface higher than the backside of the semiconductor substrate and lower than the first bottom surface.

17. The integrated circuit structure of claim 14, wherein the metal pad and the metal line comprise a conductive barrier layer, respectively.

18. The integrated circuit structure of claim 14, further comprising a bump overlying the metal line.

16. An integrated circuit structure comprising:

a semiconductor substrate having a front side and a backside, wherein the backside is opposite the front side;

an active device formed on the front side;

a through-substrate via (TSV) penetrating through the semiconductor substrate; and

a dielectric layer on the backside of the semiconductor substrate, wherein the dielectric layer comprises;

a metal pad overlying the TSV, wherein from a top-down perspective, all horizontal dimensions of the metal pad are greater than respective horizontal dimensions of the TSV; and

a metal line, wherein the metal line comprises a dual-damascene structure.

19. The integrated circuit structure of claim 16, wherein the metal pad comprises:

a first bottom surface contacting a top surface of the TSV; and

a second bottom surface higher than the backside of the semiconductor substrate and lower than the first bottom surface.