Apparatuses and methods including memory with top and bottom data lines
First Claim
Patent Images
1. An apparatus comprising:
- a first set of data lines;
a second set of data lines;
memory cells located in different levels of the apparatus and arranged in memory cell strings between the first and second sets of data lines, the first set of data lines used to retrieve information from a first memory cell set of the memory cells, and the second set of data lines used to retrieve information from a second memory cell set of the memory cells;
a first transistor coupled between a first memory string of the memory cell strings and a first data line of the first set of data lines;
a first select line to provide a signal to control the first transistor;
a second transistor coupled between a second memory cell string of the memory cell strings and a second data line of the second set of data lines;
a second select line to provide a signal to control the second transistor; and
a module configured to select the first and second memory cell strings in an operation of the apparatus, wherein the first memory cell string includes a first memory cell, the second memory cell string includes a second memory cell, and the module is configured to concurrently store information into the first and second memory cells.
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Abstract
Some embodiments include apparatuses and methods having a first set of data lines, a second set of data lines, and memory cells located in different levels of the apparatus. In at least one of such embodiments, the memory cells can be arranged in memory cell strings between the first and second set of data lines. Other embodiments including additional apparatuses and methods are described.
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Citations
26 Claims
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1. An apparatus comprising:
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a first set of data lines; a second set of data lines; memory cells located in different levels of the apparatus and arranged in memory cell strings between the first and second sets of data lines, the first set of data lines used to retrieve information from a first memory cell set of the memory cells, and the second set of data lines used to retrieve information from a second memory cell set of the memory cells; a first transistor coupled between a first memory string of the memory cell strings and a first data line of the first set of data lines; a first select line to provide a signal to control the first transistor; a second transistor coupled between a second memory cell string of the memory cell strings and a second data line of the second set of data lines; a second select line to provide a signal to control the second transistor; and
a module configured to select the first and second memory cell strings in an operation of the apparatus, wherein the first memory cell string includes a first memory cell, the second memory cell string includes a second memory cell, and the module is configured to concurrently store information into the first and second memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus:
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a first data line located on a first level of the apparatus; a second data line located on a second level of the apparatus; a first memory cell string coupled to the first data line, the first data line used to retrieve information from the first memory cell string; a second memory cell string coupled to the second data line, the second data line used to retrieve information from the second memory cell string; a first transistor coupled between a first memory string of the memory cell strings and a first data line of the first set of data lines; a first select line to provide a signal to control the first transistor; a second transistor coupled between a second memory cell string of the memory cell strings and a second data line of the second set of data lines; a second select line to provide a signal to control the second transistor; and a module configured to select the first and second memory cell strings in an operation of the apparatus, wherein the first memory cell string includes a first memory cell, the second memory cell string includes a second memory cell, and the module is configured to concurrently retrieve information from the first and second memory cells.
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9. An apparatus comprising:
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a first data line located on a first level of the apparatus; a second data line located on a second level of the apparatus; a first memory cell string coupled to the first data line, the first data line used to retrieve information from the first memory cell string; a second memory cell string coupled to the second data line, the second data line used to retrieve information from the second memory cell string; a module configured to select the first and second memory cell strings in an operation of the apparatus; a first transistor coupled between the first memory cell string and the first data line; a first select line to provide a signal to control the first transistor; a second transistor coupled between the second memory cell string and the second data line; a second select line to provide a signal to control the second transistor; and a module configured to select the first and second memory cell strings in an operation of the apparatus, wherein the first memory cell string includes a first memory cell, the second memory cell string includes a second memory cell, and the module is configured to concurrently store information into the first and second memory cells. - View Dependent Claims (10, 11)
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12. An apparatus comprising:
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a first data line located on a first level of the apparatus; a second data line located on a second level of the apparatus; a first memory cell string coupled to the first data line, the first data line used to retrieve information from the first memory cell string; a second memory cell string coupled to the second data line, the second data line used to retrieve information from the second memory cell string; a module configured to select the first and second memory cell strings in an operation of the apparatus; a third data line located on the first level of the apparatus; a third memory cell string coupled in the third data line; a fourth data line located on the second level of the apparatus; and a fourth memory cell string coupled to the fourth data line;
wherein the module is configured to select the third and fourth memory cell strings in the operation of the apparatus, and wherein the module is configured to concurrently store information into a first memory cell included in the first memory cell string, a second memory cell included in the second memory cell string, a third memory cell included in the third memory cell string, and a fourth memory cell included in the fourth memory cell string in the operation of the apparatus.
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13. An apparatus comprising:
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a first data line located on a first level of the apparatus; a second data line located on a second level of the apparatus; a first memory cell string coupled to the first data line, the first data line used to retrieve information from the first cell string; a second memory cell string coupled to the second data line, the second data line used to retrieve information from the second memory cell string; a module configured to select the first and second memory cell strings in an operation of the apparatus; a first transistor coupled between the first memory cell string and the first data line; a first select line to provide a signal to control the first transistor; a second transistor coupled between the second memory cell string and the second data line; and a second line to provide a signal to control the first transistor, wherein the module is configured to concurrently retrieve information from a first memory cell included in the first memory cell string a second memory cell included in the second memory cell string, a third memory cell included in a third memory cell string, and a fourth memory cell included in a fourth memory cell string in operation of the apparatus.
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14. An apparatus comprising:
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memory cells arranged in rows including a first row and a second row, the memory cells including a first memory cell set located in the first row and a second memory cell set located in the second row; a first set of data lines; a second set of data lines; and a module configured to perform at least one of concurrently retrieve information from the first and second memory cell sets through the first and second sets of data lines in a first operation of the apparatus, and concurrently store information into the first and second memory cell sets through the first and second sets of data lines in a second operation of the apparatus. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A method comprising:
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selecting a first memory cell string associated with a first data line of a device in an operation of the device, the first data line located on a first level of the device; selecting a second memory cell string associated with a second data line of the device in the operation of the device, the second data line located on a level of the device retrieving information from a first memory cell in the first memory cell string through the first data line; retrieving information from a second memory cell in the second memory cell string through the second data line, wherein retrieving the information from the first memory cell and retrieving information from the second memory cell are performed concurrently.
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21. A method comprising:
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selecting a first memory cell string associated with a first data line of a device in an operation of the device, the first data line located on a first level of the device; selecting a second memory cell string associated with a second data line of the device in the operation of the device, the second data line located on a second level of the device retrieving information from a first memory cell in the first memory cell string through the first data line; retrieving information from a second memory cell in the second memory cell string through the second data line; storing information into the first memory cell in an additional operation device; and storing information into the second memory cell in the additional operation of the device, wherein storing information into the first memory cell and storing information into the second memory cell are performed concurrently.
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22. A method comprising:
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selecting first memory cell strings associated with a first set of data lines in an operation of a device, the first memory cell strings including a first memory cell set located in a first row of memory cells of the device, the first set of data lines used to retrieve information from the first memory cell strings; selecting second memory cell strings associated with a second set of data lines in the operation of the device, the second memory cell strings including a second memory cell set located in a second row of memory cells of the device, the second set of data lines used to retrieve information from the second memory cell strings; and performing at least one of a first operation and a second operation, wherein performing the first operation includes concurrently storing information into the first and second memory cell sets, and performing the second operation includes concurrently retrieving information from the first and second memory cell sets. - View Dependent Claims (23, 24, 25, 26)
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Specification