Split data error correction code circuits
First Claim
Patent Images
1. A split data error correction code (ECC) circuit comprising:
- a control circuit coupled to an error correction code (ECC) circuit; and
wherein the ECC circuit is adapted to generate at least one ECC code from user data of a first physical sector during a data access, and where the split data ECC circuit is adapted to write the at least one ECC code to a second physical sector if the data access is a write access and to compare the at least one generated ECC code with at least one ECC code stored in a second physical sector if the data access is a read access.
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Abstract
Split data error correction code (ECC) circuits including a control circuit coupled to an error correction code (ECC) circuit. The ECC circuit is adapted to generate at least one ECC code from user data of a first physical sector during a data access. The split data ECC circuit is adapted to write the at least one ECC code to a second physical sector if the data access is a write access and to compare the at least one generated ECC code with at least one ECC code stored in a second physical sector if the data access is a read access.
64 Citations
20 Claims
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1. A split data error correction code (ECC) circuit comprising:
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a control circuit coupled to an error correction code (ECC) circuit; and wherein the ECC circuit is adapted to generate at least one ECC code from user data of a first physical sector during a data access, and where the split data ECC circuit is adapted to write the at least one ECC code to a second physical sector if the data access is a write access and to compare the at least one generated ECC code with at least one ECC code stored in a second physical sector if the data access is a read access. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A split data error correction code (ECC) circuit comprising:
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a storage circuit; an error correction code (ECC) circuit coupled to the storage circuit; and a control circuit coupled to the ECC circuit and coupled to the storage circuit; wherein the ECC circuit is adapted to generate at least one ECC code from user data of a first physical sector during a write access of the first physical sector and to write the at least one ECC code to the storage circuit; and wherein the split data ECC circuit is adapted to write the at least one ECC code from the storage circuit to a second physical sector during a write access of the second physical sector. - View Dependent Claims (12, 13, 14, 15)
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16. A split data error correction code (ECC) circuit comprising:
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a storage circuit; an error correction code (ECC) circuit coupled to the storage circuit; and a control circuit coupled to the ECC circuit and coupled to the storage circuit; wherein the ECC circuit is adapted to generate at least one ECC code from user data of a first physical sector during a read access of the first physical sector and to write the at least one ECC code to the storage circuit; and wherein the split data ECC circuit is adapted to read stored ECC data from a second physical sector during a read access of the second physical sector, and to compare the at least one ECC code to the stored ECC data from the second physical sector to detect data errors in the user data of the first physical sector. - View Dependent Claims (17, 18, 19, 20)
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Specification