System and method for integrated circuit calibration

• US 8,793,091 B2
• Filed: 04/10/2008
• Issued: 07/29/2014
• Est. Priority Date: 04/10/2008
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Ku, Ting, Yu, Shifeng, Smith, Brian
• Primary Examiner(s): Lau, Tung S
• Assistant Examiner(s): SUN, XIUQIN
• Application Number:
  US12/101,029
• Publication Number:
  US 20090259425A1
• Time in Patent Office: 2,301 Days
• Field of Search: 702/99, 327/108, 600/547, 326/30, 713/171, 705/27, 365/189.05
• US Class Current: 702/99
• CPC Class Codes: G01K 15/00 Testing or calibrating of thermometers
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching

Abstract

A system and method for calibrating an integrated circuit. The method includes configuring a first impedance for a first output of the integrated circuit according to a first configuration code and measuring a first voltage at the first output which corresponds to the first configuration code. The method further includes configuring a second impedance for a second output of the integrated circuit according to a second configuration code and measuring a second voltage at the second output which corresponds to the second configuration code. A determination of which of the first voltage and the second voltage is nearest to a predetermined voltage value. Based on the voltage determination, the integrated circuit is configured according a code of said first and second codes that corresponds to the voltage nearest to the predetermined voltage.

Claims

1. A method for calibrating an integrated circuit, comprising:

configuring a first impedance for a first output driver of said integrated circuit according to a first configuration code;

measuring a first voltage at the output of said first output driver, wherein said first voltage corresponds to said first configuration code;

configuring a second impedance for a second output driver of said integrated circuit according to a second configuration code;

measuring a second voltage at the output of said second output driver, wherein said second voltage corresponds to said second configuration code;

comparing said output of said first output driver and said output of said second output driver to a predetermined voltage value;

determining which of said first voltage and said second voltage is nearest to said predetermined voltage value; and

configuring said integrated circuit according to a code of said first and second codes that corresponds to said voltage nearest to said predetermined voltage.

2. The method as described in claim 1 wherein said measuring of said first voltage and said second voltage is performed by an integrated circuit tester coupled to said integrated circuit.

3. The method as described in claim 1 wherein said configuring comprises blowing a fuse disposed with said integrated circuit that controls said first and second impedance.

4. The method as described in claim 3 wherein said fuse is coupled to a pull up circuit.

5. The method as described in claim 3 wherein said fuse is coupled to a pull down circuit.

6. The method as described in claim 1 wherein said configuring said first and second impedance for said first and second output is via pull up circuits.

7. The method as described in claim 1 wherein said configuring said first and second impedance for said first and second output is via pull down circuits.

8. The method as described in claim 1 wherein said first and second output is a general purpose input/output (GPIO).

9. The method as described in claim 1 wherein said first code is part of a first set of codes and said second code is part of a second set of codes.

10. The method as described in claim 1 wherein said first output driver is coupled to a first output pin of said integrated circuit and said second output driver is coupled to a second output pin of said integrated circuit.

11. The method as described in claim 1 further comprising:

generating an offset code based on voltage and temperature variations corresponding to said integrated circuit.

12. The method as described in claim 11 wherein said configuring said integrated circuit comprises configuring said integrated circuit according to a code of said first and second codes that corresponds to said voltage nearest to said predetermined voltage, and offset by said offset code.

13. The method as described in claim 11 wherein said voltage and temperature variations are tracked in a voltage and temperature sensor.

14. The method as described in claim 13 wherein said voltage and/or temperature sensor comprises a polysilicon resistor.

15. A system for calibrating an integrated circuit comprising:

an interface for coupling an integrated circuit to be calibrated;

an impedance configuration module operable to issue a first code and a second code to a first driver and a second driver, respectively, of said integrated circuit wherein said first code and said second code are associated with a first impedance value and a second impedance value of said first and second drivers of said integrated circuit;

a voltage measurer for measuring a first voltage and a second voltage at outputs of said first and second drivers of said integrated circuit;

a temperature sensor for tracking temperature variations of said integrated circuit;

a code determiner operable to compare said first voltage and said second voltage to a predetermined value and to determine which voltage of said first voltage corresponding to said first code and said second voltage corresponding to said second code is closer to said predetermined voltage, and to generate signal based on said temperature variations; and

an integrated circuit configuration module operable to configure said first and second drivers of said integrated circuit according to said first code or said second code based on whether said first voltage or said second voltage is closest to said predetermined voltage, and offset by said signal.

16. The system of claim 15 wherein said code determiner determines a third code via interpolation.

17. The system of claim 15 wherein said first driver of said integrated circuit comprises a pull up circuit and wherein said impedance configuration module issues said first code to said pull up circuit.

18. The system of claim 17 wherein said integrated circuit configuration module is operable to configure said integrated circuit by blowing a fuse coupled to said pull up circuit.

19. The system of claim 15 wherein said first driver of said integrated circuit comprises a pull down circuit and wherein said impedance configuration module is operable to issue said first code to said pull down circuit.

20. The system of claim 19 wherein said integrated circuit configuration module is operable to configure said integrated circuit by blowing a fuse coupled to said pull down circuit.

21. The system of claim 15 wherein at least one output of said integrated circuit is a general purpose input output (GPIO).

22. A programmable system on a chip (SoC) comprising:

a plurality of outputs;

a plurality of drivers respectively coupled to said plurality of outputs, each driver comprising;

a pull up circuit coupled to a respective output;

a pull down circuit coupled to said respective output;

a plurality of impedance configuration circuits, wherein each of said plurality of impedance configuration circuits is coupled to a respective driver of said plurality of drivers and wherein each of said impedance configuration circuits is operable to configure a different impedance of each respective pull up circuit and each respective pull down circuit of said respective driver of said plurality of drivers;

a first fuse operable to fix the impedance configuration of each pull up circuit based on a calibration result performed on said SoC during testing;

a second fuse operable to fix the impedance configuration of each pull down circuit based on said calibration result;

a voltage and/or temperature sensor operable to track voltage and temperature variations of the SoC, and

a calibration circuit operable to calibrate the plurality of drivers based on said tracked voltage and temperature variations and a predetermined voltage, wherein said calibration circuit is operable to calibrate said plurality of drivers based on a comparison of said tracked voltage and said predetermined voltage.

23. The SoC as described in claim 22 further comprising a Graphical Processing Unit (GPU).

24. The SoC as described in claim 22 further comprising a video processor.

25. The SoC as described in claim 22 wherein said voltage and/or temperature sensor comprises a polysilicon resistor which facilitates said tracking of voltage and temperature variations during operation of the SoC.

26. The SoC as described in claim 25 wherein said polysilicon resistor does not utilize a pin or ball of the SoC.