Atomic operations

• US 8,793,404 B2
• Filed: 06/11/2012
• Issued: 07/29/2014
• Est. Priority Date: 11/02/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ajanovic, Jasmin, Wagh, Mahesh, Sethi, Prashant, Sharma, Debendra Das, Harriman, David, Rosenbluth, Mark, Bhatt, Ajay, Barry, Peter, Rodgers, Scott Dion, Vasudevan, Anil, Muthrasanallur, Sridhar, Akiyama, James, Blankenship, Robert, Falik, Ohad, Mendelson, Abraham, Pardo, Ilan, Tamari, Eran, Weissmann, Eliezer, Shamia, Doron
• Primary Examiner(s): Alrobaye, Idriss N
• Assistant Examiner(s): MARTINEZ, DAVID E
• Application Number:
  US13/493,606
• Publication Number:
  US 20120254563A1
• Time in Patent Office: 778 Days
• Field of Search: None
• US Class Current: 710/5
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4265 on a point to point bus G06F13/4247, G06F13/4282 take precedence
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Claims

1. A method comprising:

generating a request packet with a device, the request packet including a reference to an atomic operation and a packet identifier, wherein the atomic operation includes a read, modify, write (RMW) operation selected from a set comprising a two'"'"'s complement add operation, a swap operation, and a test and swap operation;

storing an outstanding reference to the request packet in the device, the outstanding reference including a reference to the packet identifier;

transmitting the request packet over a point-to-point, coherent fabric to a controller utilizing a layered protocol stack; and

retiring the outstanding reference to the request packet stored in the device in response to receiving a response message with the device from the controller.

2. The method of claim 1, further comprising

receiving the request packet with the controller;

determining the atomic operation from the request packet in response to receiving the request packet with the controller;

servicing the atomic operation in response to determining the atomic operation from the request packet;

transmitting a response message in response to servicing the atomic operation, the response message including the reference to the packet identifier.

3. The method of claim 1, wherein the set further comprises a BitSet operation, and a BitClear operation.

4. An apparatus comprising:

an integrated circuit including,

a protocol stack including layered protocol stack adapted to assemble a request packet to include a reference to an atomic operation and a packet identifier, wherein the atomic operation includes a read, modify, write (RMW) operation selected from a set comprising a two'"'"'s complement add operation, a swap operation, and a test and swap operation;

outstanding logic adapted to hold an outstanding reference to the request packet, the outstanding reference including a reference to the packet identifier;

the layered protocol stack adapted to transmit the request packet over a point-to-point, coherent fabric to a controller; and

retirement logic adapted to retire the outstanding reference to the request packet from the outstanding logic in response to receiving a response message from the controller.

5. The apparatus of claim 4, further comprising:

the controller adapted to be coupled to the integrated circuit, the controller including,

a layered protocol stack adapted to receive the request packet and to determine the atomic operation from the request packet in response to receiving the request packet;

logic to service the atomic operation in response to determining the atomic operation from the request packet;

wherein the layered protocol stack is further adapted to transmit the response message in response to the logic servicing the atomic operation, the response message including the reference to the packet identifier.

6. The apparatus of claim 4, wherein the set further comprises a BitSet operation, and a BitClear operation.