Adaptive error correction for non-volatile memories

• US 8,793,558 B2
• Filed: 08/27/2012
• Issued: 07/29/2014
• Est. Priority Date: 08/27/2012
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Cunningham, Jeffrey C., Gasquet, Horacio P., Scouller, Ross S., Cabassi, Marco A.
• Primary Examiner(s): Rizk, Sam
• Application Number:
  US13/595,282
• Publication Number:
  US 20140059398A1
• Time in Patent Office: 701 Days
• Field of Search: 714/773, 714/774, 365/185.2
• US Class Current: 714/774
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

Adaptive error correction for non-volatile memories is disclosed that dynamically adjusts sense amplifier read detection windows. Memory control circuitry uses error correction code (ECC) routines to detect bit errors that are non-correctable using these ECC routines. The memory control circuitry then dynamically adjusts sense amplifier read detection windows to allow for correct data to be determined. Corrected data can then be output to external circuitry. The corrected data can also be stored for later access when subsequent read operations attempt to access address locations that previously suffered bit failures. The adaptive error correction can also be used with respect to memories that are not non-volatile memories.

Claims

1. A memory system, comprising:

an array of memory cells;

sense amplifier circuitry configured to provide data output signals associated with sensed voltage levels for a plurality of memory cells within the array of memory cells, the sense amplifier circuitry having read detection windows for the sensed voltage levels; and

memory control circuitry configured to receive the data output signals and to identify and correct bit errors within the data output signals by applying at least one error correction control (ECC) routine, the memory control circuitry being further configured to vary the read detection windows by adjusting at least one operating parameter when an identified bit error is not correctable by the at least one ECC routine and to cause the sense amplifier circuitry to re-sense voltage levels for the plurality of memory cells using the adjusted at least one operating parameter; and

data storage circuitry;

wherein the memory control circuitry is further configured to vary the read detection windows until detected but uncorrectable bit errors are corrected and to output corrected data, to store the corrected data and an address for the not correctable error in the data storage circuitry, and to access the stored corrected data if a subsequent read operation addresses data from the address.

2. The memory system of claim 1, wherein the at least one ECC routine is configured to identify single-bit errors and double-bit errors and is configured to correct only single-bit errors.

3. The memory system of claim 1, wherein the array of memory cells comprises an array of non-volatile memory (NVM) cells, and wherein the at least one operating parameter comprises a current reference signal for the sense amplifier circuitry.

4. The memory system of claim 3, further comprising reference current generation circuitry configured to provide the current reference signal to the sense amplifier circuitry based upon a reference current control signal, and wherein the memory control circuitry is further configured to adjust the reference current control signal when an identified bit error is not correctable.

5. The memory system of claim 4, wherein the memory control circuitry is configured to adjust the reference current control signal so that the read detection windows are varied across an adjustment window.

6. The memory systems of claim 1, wherein the array of memory cells comprises an array of non-volatile memory (NVM) cells, and wherein the at least one operating parameter comprises a read voltage level applied to the plurality of the memory cells.

7. The memory system of claim 1, wherein the memory control circuitry is further configured to report a read failure if an adjustment limit has been reached for the at least one operating parameter.

8. The memory system of claim 1, wherein the memory control circuitry is further configured to assert a hold command to external circuitry when uncorrectable bit errors are detected and to de-assert the hold command once corrected data is determined.

9. A method for reading data from a memory system, comprising:

sensing voltage levels for a plurality of memory cells within an array of memory cells using sense amplifier circuitry, the sense amplifier circuitry having read detection windows for the sensed voltage levels;

applying an error correction code (ECC) routine to identify and correct bit errors within data output signals associated with sensed voltage levels for the plurality of the memory cells;

varying the read detection windows by adjusting at least one operating parameter when an identified bit error is not correctable using the ECC routine and determining an address for the not correctable error; and

repeating the sensing, applying, and varying steps until the not correctable error is correctable using the ECC routine;

outputting corrected data;

storing the corrected data and the address in data storage circuitry; and

accessing the stored corrected data if a subsequent read operation addresses data from the address.

10. The method of claim 9, further comprising reporting a read failure and ending the repeating step if an adjustment limit has been reached for the at least one operating parameter.

11. The method of claim 9, wherein the ECC routine is configured to identify single-bit errors and double-bit errors and to correct only single-bit errors.

12. The method of claim 9, wherein the array of memory cells comprises an array of non-volatile memory (NVM) cells, and wherein the varying step comprises varying the read detection windows by adjusting a current reference signal for the sense amplifier circuitry.

13. The method of claim 9, wherein the array of memory cells comprises an array of non-volatile memory (NVM) cells, and wherein the varying step comprises varying the read detection windows by adjusting a read voltage level applied to the plurality of memory cells.

14. The method of claim 9, further comprising asserting a hold command to external circuitry when an uncorrectable bit error is detected, and de-asserting the hold command once all identified bit errors are correctable using the ECC routine.