Fan out build up substrate stackable package and method
First Claim
1. A fan out build up substrate stackable package comprising:
- an integrated circuit chip comprising an active surface comprising a bond pad;
a package body directly contacting and enclosing sides of the integrated circuit chip, the package body comprising a first surface coplanar with the active surface of the integrated circuit chip;
a first buildup dielectric layer comprising a first surface applied to the active surface of the integrated circuit chip and the first surface of the package body;
a first circuit pattern electrically connected to the bond pad, the first circuit pattern comprising a via capture pad formed within the first buildup dielectric layer and a trace embedded in the first buildup dielectric layer at a second surface of the first buildup dielectric layer; and
a via capture pad aperture extending through the package body but not through the first buildup dielectric layer and exposing the via capture pad, wherein the package body further comprises a second surface, the via capture pad aperture extending from the second surface to and ending at the first surface of the package body;
further comprising a backside warpage control layer applied to the second surface of the package body.
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Accused Products
Abstract
A fan out build up substrate stackable package includes an electronic component having an active surface including a bond pad. A package body encloses the electronic component, the package body having a first surface coplanar with the active surface of the electronic component. A buildup dielectric layer is applied to the active surface of the electronic component and the first surface of the package body. A circuit pattern is formed within the first buildup dielectric layer and electrically connected to the bond pad, the first circuit pattern including via capture pads. Via capture pad apertures extend through the package body and expose the via capture pads. In this manner, direct connection to the first circuit pattern, i.e., the first metal layer, of the fan out build up substrate stackable package is facilitated. Further, the fan out build up substrate stackable package is extremely thin resulting in extremely thin stacked assemblies.
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Citations
17 Claims
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1. A fan out build up substrate stackable package comprising:
- an integrated circuit chip comprising an active surface comprising a bond pad;
a package body directly contacting and enclosing sides of the integrated circuit chip, the package body comprising a first surface coplanar with the active surface of the integrated circuit chip;
a first buildup dielectric layer comprising a first surface applied to the active surface of the integrated circuit chip and the first surface of the package body;
a first circuit pattern electrically connected to the bond pad, the first circuit pattern comprising a via capture pad formed within the first buildup dielectric layer and a trace embedded in the first buildup dielectric layer at a second surface of the first buildup dielectric layer; and
a via capture pad aperture extending through the package body but not through the first buildup dielectric layer and exposing the via capture pad, wherein the package body further comprises a second surface, the via capture pad aperture extending from the second surface to and ending at the first surface of the package body;
further comprising a backside warpage control layer applied to the second surface of the package body. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
- an integrated circuit chip comprising an active surface comprising a bond pad;
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11. A fan out build up substrate stackable package comprising:
- an electronic component comprising an active surface comprising a bond pad;
a dielectric film comprising a first surface applied to the active surface of the electronic component including the bond pad, the dielectric film further comprising a second surface;
a package body enclosing the electronic component and the dielectric film, the package body comprising a first surface coplanar with the second surface of the dielectric film;
an integrally plated first circuit pattern formed within the dielectric film and the package body and electrically connected to the bond pad, the first circuit pattern comprising a via capture pad formed within the package body and a trace embedded within the dielectric film at the second surface of the dielectric film and within the package body at the first surface of the package body; and
a via capture pad aperture extending through the package body and exposing the via capture pad;
wherein the first circuit pattern further comprises;
a bond pad via formed within the dielectric film and electrically connected to the bond pad, the trace electrically connecting the bond pad via to the via capture pad. - View Dependent Claims (12, 13, 14)
- an electronic component comprising an active surface comprising a bond pad;
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15. A fan out build up substrate stackable package comprising:
- a plated via capture pad;
an electronic component comprising an active surface comprising adhesive thereon;
a package body encapsulating and directly contacting the via capture pad and sides of the electronic component;
a via capture pad aperture extending through the package body and aligned with the via capture pad;
a first buildup dielectric layer comprising a first surface applied to a first surface of the package body, the via capture pad, and the adhesive; and
a first circuit pattern formed in the first buildup dielectric layer, the first circuit pattern being electrically connected to a bond pad on the active surface of the electronic component and to the via capture pad, the first circuit pattern comprising a trace embedded in the first buildup dielectric layer at a second surface of the first buildup dielectric layer, where the embedded trace runs parallel to the second surface of the first buildup dielectric layer, further comprising;
a stacked flip chip electronic component mounted to an inactive surface of the electronic component through via terminals of the electronic component that terminate respective conductive vias extending through the electronic component, wherein the package body further encapsulates the stacked flip chip electronic component. - View Dependent Claims (16, 17)
- a plated via capture pad;
Specification