Fan out build up substrate stackable package and method

• US 8,796,561 B1
• Filed: 10/05/2009
• Issued: 08/05/2014
• Est. Priority Date: 10/05/2009
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Scanlan, Christopher M., St. Amand, Roger D., Kim, Jae Dong
• Primary Examiner(s): Nguyen, Chau N
• Assistant Examiner(s): VARGHESE, ROSHN K
• Application Number:
  US12/573,466
• Time in Patent Office: 1,765 Days
• Field of Search: 174/266, 174/534, 174/260, 174/261, 361/761, 361/762, 361/763, 361/764, 257/698, 257/734
• US Class Current: 174/534
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73259 Bump and HDI connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2203/1469 : Circuit made after mounting or encapsulation of the components
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: H05K 3/465 : by applying an insulating layer having channels for the next circuit layer

Abstract

A fan out build up substrate stackable package includes an electronic component having an active surface including a bond pad. A package body encloses the electronic component, the package body having a first surface coplanar with the active surface of the electronic component. A buildup dielectric layer is applied to the active surface of the electronic component and the first surface of the package body. A circuit pattern is formed within the first buildup dielectric layer and electrically connected to the bond pad, the first circuit pattern including via capture pads. Via capture pad apertures extend through the package body and expose the via capture pads. In this manner, direct connection to the first circuit pattern, i.e., the first metal layer, of the fan out build up substrate stackable package is facilitated. Further, the fan out build up substrate stackable package is extremely thin resulting in extremely thin stacked assemblies.

Claims

1. A fan out build up substrate stackable package comprising:

an integrated circuit chip comprising an active surface comprising a bond pad;

a package body directly contacting and enclosing sides of the integrated circuit chip, the package body comprising a first surface coplanar with the active surface of the integrated circuit chip;

a first buildup dielectric layer comprising a first surface applied to the active surface of the integrated circuit chip and the first surface of the package body;

a first circuit pattern electrically connected to the bond pad, the first circuit pattern comprising a via capture pad formed within the first buildup dielectric layer and a trace embedded in the first buildup dielectric layer at a second surface of the first buildup dielectric layer; and

a via capture pad aperture extending through the package body but not through the first buildup dielectric layer and exposing the via capture pad, wherein the package body further comprises a second surface, the via capture pad aperture extending from the second surface to and ending at the first surface of the package body;

further comprising a backside warpage control layer applied to the second surface of the package body.

2. The fan out build up substrate stackable package of claim 1 wherein the integrated circuit chip further comprises an inactive surface coplanar with the second surface of the package body.

3. The fan out build up substrate stackable package of claim 1 wherein the integrated circuit chip further comprises an inactive surface, the second surface of the package body being above and spaced apart from the inactive surface of the integrated circuit chip.

4. The fan out build up substrate stackable package of claim 1 wherein the backside warpage control layer has a thermal coefficient of expansion similar to the first buildup dielectric layer.

5. The fan out build up substrate stackable package of claim 1 wherein the backside warpage control layer covers only a central region of the second surface of the package body.

6. The fan out build up substrate stackable package of claim 1 wherein the first circuit pattern further comprises:

a bond pad via extending entirely through the first buildup dielectric layer and being electrically connected to the bond pad, wherein the trace electrically connects the bond pad via to the via capture pad.

7. The fan out build up substrate stackable package of claim 1 further comprising:

a second buildup dielectric layer applied to the first buildup dielectric layer and to the first circuit pattern; and

a second circuit pattern formed within the second buildup dielectric layer and electrically connected to the first circuit pattern, the second circuit pattern comprising lands.

8. The fan out build up substrate stackable package of claim 1 wherein the via capture pad comprises a first surface coplanar with the first surface of the package body and the active surface of the integrated circuit chip.

9. The fan out build up substrate stackable package of claim 8 further comprising a via capture pad pin protruding from the first surface of the via capture pad and into the via capture pad aperture.

10. The fan out build up substrate stackable package of claim 1 wherein the via capture pad extends entirely through the first buildup dielectric layer and into the package body, the via capture pad comprising a first surface between the first surface of the package body and a second surface of the package body.

11. A fan out build up substrate stackable package comprising:

an electronic component comprising an active surface comprising a bond pad;

a dielectric film comprising a first surface applied to the active surface of the electronic component including the bond pad, the dielectric film further comprising a second surface;

a package body enclosing the electronic component and the dielectric film, the package body comprising a first surface coplanar with the second surface of the dielectric film;

an integrally plated first circuit pattern formed within the dielectric film and the package body and electrically connected to the bond pad, the first circuit pattern comprising a via capture pad formed within the package body and a trace embedded within the dielectric film at the second surface of the dielectric film and within the package body at the first surface of the package body; and

a via capture pad aperture extending through the package body and exposing the via capture pad;

wherein the first circuit pattern further comprises;

a bond pad via formed within the dielectric film and electrically connected to the bond pad, the trace electrically connecting the bond pad via to the via capture pad.

12. The fan out build up substrate stackable package of claim 11 further comprising:

a buildup dielectric layer applied to the first surface of the package body, the second surface of the dielectric film, and to the first circuit pattern; and

a second circuit pattern formed within the buildup dielectric layer and electrically connected to the first circuit pattern, the second circuit pattern comprising lands.

13. The fan out build up substrate stackable package of claim 11, wherein the dielectric film comprises a planar side surface extending between the first and second surfaces of the dielectric film.

14. The fan out build up substrate stackable package of claim 11, wherein:

the electronic component comprises a side surface extending between the active surface and an inactive surface of the electronic component;

the dielectric film comprises a side surface extending between the first and second surfaces of the dielectric film; and

the side surface of the electronic component is coplanar with the side surface of the dielectric film.

15. A fan out build up substrate stackable package comprising:

a plated via capture pad;

an electronic component comprising an active surface comprising adhesive thereon;

a package body encapsulating and directly contacting the via capture pad and sides of the electronic component;

a via capture pad aperture extending through the package body and aligned with the via capture pad;

a first buildup dielectric layer comprising a first surface applied to a first surface of the package body, the via capture pad, and the adhesive; and

a first circuit pattern formed in the first buildup dielectric layer, the first circuit pattern being electrically connected to a bond pad on the active surface of the electronic component and to the via capture pad, the first circuit pattern comprising a trace embedded in the first buildup dielectric layer at a second surface of the first buildup dielectric layer, where the embedded trace runs parallel to the second surface of the first buildup dielectric layer, further comprising;

a stacked flip chip electronic component mounted to an inactive surface of the electronic component through via terminals of the electronic component that terminate respective conductive vias extending through the electronic component, wherein the package body further encapsulates the stacked flip chip electronic component.

16. The fan out build up substrate stackable package of claim 15 further comprising solder on the via capture pad.

17. The fan out build up substrate stackable package of claim 15 further comprising:

a plurality of via capture pads comprising the via capture pad;

a stacked wirebond electronic component comprising an inactive surface mounted to an inactive surface of the electronic component; and

bond wires electrically connecting bond pads on an active surface of the stacked wirebond electronic component to the via capture pads, wherein the package body further encapsulates the stacked wirebond electronic component and the bond wires.