Low voltage tunnel field-effect transistor (TFET) and method of making same

• US 8,796,733 B2
• Filed: 08/09/2011
• Issued: 08/05/2014
• Est. Priority Date: 08/09/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation, University of Notre DAME Du Lac
• Original Assignee: International Business Machines Corporation, University of Notre DAME Du Lac
• Inventors: Fay, Patrick, Xing, Huili (Grace), Seabaugh, Alan C., Zhou, Guangle, Lu, Yeqing, Wistey, Mark A., Koswatta, Siyuranga
• Primary Examiner(s): Dickey, Thomas L
• Application Number:
  US13/206,187
• Publication Number:
  US 20120032227A1
• Time in Patent Office: 1,092 Days
• Field of Search: 257/17, 257/25, 257/183.01
• US Class Current: 257/183
• CPC Class Codes: H01L 29/7391 Gated diode structures

Abstract

A low voltage tunnel field effect transistor includes a p-n tunnel junction, a gate-dielectric, a gate, a source-contact, and a drain-contact. The p-n tunnel junction includes a depletion region interfacing together a source-layer and a drain-layer. The depletion region includes a source-tunneling-region of the source-layer and a drain-tunneling-region of the drain-layer. When no external electric field is imposed, the depletion region of the p-n tunnel junction has an internal electric field that substantially points towards the source-tunneling-region and the drain-tunneling-region. The gate-dielectric is interfaced directly onto the drain-tunneling-region such that the drain-tunneling-region is between the source-tunneling-region and the gate-dielectric. The gate is interfaced onto the gate-dielectric such that the gate is configured to impose an external electric field which is oriented substantially in parallel to the internal electric field of the depletion region.

Claims

1. A tunnel field-effect transistor comprising:

a p-n tunnel junction comprising;

a source-layer comprising a source-tunneling-region;

a drain-layer comprising a drain-tunneling-region and underneath the drain-layer an air-bridge that substantially restricts electrical conduction between the drain-layer and the source-layer through the drain-tunneling-region and the source-tunneling-region; and

a depletion region formed at the interface of the source-tunneling-region and drain-tunneling-region in which the depletion region exhibits an internal electric field that substantially points between the source-tunneling-region and drain-tunneling-region when no external electric field is imposed;

a gate-dielectric interfaced onto the drain-tunneling-region such that the drain-tunneling-region is immediately between the source-tunneling-region and the gate-dielectric;

a gate interfaced onto the gate-dielectric wherein the gate is configured to impose an external electric field which is oriented substantially in parallel to the internal electric field of the depletion region;

a source-contact coupled to the source-layer; and

a drain-contact coupled to the drain-layer.

2. A tunnel field-effect transistor as defined in claim 1, wherein when the external electric field is imposed substantially in parallel to the internal electric field of the depletion region and when the external electric field is pointed in a substantially same direction as that of the internal electric field of the depletion region, then tunneling from the source-tunneling-region to the drain-tunneling-region across the depletion region is promoted.

3. A tunnel field-effect transistor as defined in claim 2, wherein tunneling between the source-tunneling-region and the drain-tunneling-region is promoted substantially normal to a gate/dielectric-interface.

4. A tunnel field-effect transistor as defined in claim 1, wherein the tunnel field-effect transistor does not have an intrinsic layer between the source-tunneling-region and the drain-tunneling-region.

5. A tunnel field-effect transistor as defined in claim 1, wherein the gate-dielectric is not interfaced across the depletion region.

6. A tunnel field-effect transistor as defined in claim 1, wherein gate-dielectric is not directly contacted to the depletion region.

7. A tunnel field-effect transistor as defined in claim 1, wherein the source-layer comprises a p-doped Al_xGa_1-xSb source-layer and the drain-layer comprises an n-doped InAs drain-layer wherein the subscript x is between 0 and 1.

8. A tunnel field-effect transistor as defined in claim 1 further comprises a substrate on the source-layer.

9. A tunnel field-effect transistor as defined in claim 1, wherein the source-layer and drain-layer comprise substantially identical semiconductor material but have respectively different doping types.

10. A tunnel field-effect transistor as defined in claim 1 wherein the gate-dielectric exhibits a dielectric constant greater than that of silicon oxide.

11. A tunnel field-effect transistor as defined in claim 1, wherein a valence band edge of the source-tunneling-region substantially is within about 100 meV that of a conduction band edge of the drain-tunneling-region.

12. A tunnel field-effect transistor as defined in claim 1, wherein the source-layer or drain-layer comprise a semiconductor composition selected from the group consisting of Group III-V compositions, Group II-VI compositions, and Group IV compositions.

13. A tunnel field-effect transistor as defined in claim 1, further comprising a moat around the tunnel field-effect transistor.

14. A tunnel field-effect transistor as defined in claim 13, wherein the moat substantially electrically isolates the tunnel field-effect transistor and substantially eliminates conduction below the drain contact.

15. A tunnel field-effect transistor as defined in claim 1, further comprising a passivation layer covering over the tunnel field-effect transistor.

16. A tunnel field-effect transistor comprising:

a p-n tunnel junction comprising;

a source-layer comprising a p-doped InP source-layer and a source-tunneling-region;

a drain-layer comprising an n-doped In_xGa_1-xAs drain-layer wherein the subscript x is between 0 and 1 and a drain-tunneling-region; and

a depletion region formed at the interface of the source-tunneling-region and drain-tunneling-region in which the depletion region exhibits an internal electric field that substantially points between the source-tunneling-region and drain-tunneling-region when no external electric field is imposed;

a gate-dielectric interfaced onto the drain-tunneling-region such that the drain-tunneling-region is immediately between the source-tunneling-region and the gate-dielectric;

a gate interfaced onto the gate-dielectric wherein the gate is configured to impose an external electric field which is oriented substantially in parallel to the internal electric field of the depletion region;

a source-contact coupled to the source-layer; and

a drain-contact coupled to the drain-layer.