Fin-like field effect transistor (FinFET) device and method of manufacturing same

• US 8,796,759 B2
• Filed: 07/15/2010
• Issued: 08/05/2014
• Est. Priority Date: 07/15/2010
• Status: Active Grant

• Current Assignee: Parabellum Strategic Opportunities Fund LLC (Parabellum Capital LLC)
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Perng, Tsu-Hsiu, Yeh, Chih Chieh, Chang, Chih-Sheng, Chen, Tzu-Chiang, Ho, Chia-Cheng
• Primary Examiner(s): Quach, Tuan N.
• Application Number:
  US12/837,093
• Publication Number:
  US 20120012932A1
• Time in Patent Office: 1,482 Days
• Field of Search: 257/288, 257/328, 257/336, 257/401, 257/E29.2, 257/E29.201, 257/19, 257/E29.267, 438/157, 438/279
• US Class Current: 257/328
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed on a portion of the fin structure. The gate structure traverses the fin structure and separates a source region and a drain region of the fin structure, the source and drain region defining a channel therebetween. The source and drain region of the fin structure include a strained source and drain feature. The strained source feature and the strained drain feature each include: a first portion having a first width and a first depth; and a second portion disposed below the first portion, the second portion having a second width and a second depth. The first width is greater than the second width, and the first depth is less than the second depth.

Claims

1. A FinFET device comprising:

a semiconductor substrate;

a fin structure disposed over the semiconductor substrate;

a gate structure disposed on a portion of the fin structure, the gate structure traversing the fin structure, wherein the gate structure separates a source region and a drain region of the fin structure, the source and drain region defining a channel therebetween; and

the source and drain region of the fin structure including a strained source and drain feature, wherein the strained source feature and the strained drain feature each include;

a first portion having a first width and a first depth, wherein the first portion directly interfaces with the fin structure, and

a second portion disposed below the first portion, the second portion having a second width defined by a first sidewall and a second sidewall, wherein the first and second sidewalls are substantially perpendicular to a top surface of the semiconductor substrate, and wherein the second portion has a second depth, wherein the first width is greater than the second width and the first depth is less than the second depth, wherein the second sidewall of the second portion directly interfaces with the fin structure, wherein the first and second portions are formed of entirely the same material.

2. The FinFET device of claim 1 including seal spacers disposed on sidewalls of the gate structure and traversing the fin structure, wherein the first portion of the source and drain features is spaced away from the channel by a distance that is approximately equal to a thickness of one of the seal spacers.

3. The FinFET device of claim 2 wherein the first portion of the strained source and drain feature includes a portion that directly contacts the seal spacers.

4. The FinFET device of claim 1 wherein the strained source and drain feature includes silicon germanium.

5. The FinFET device of claim 1 wherein the strained source and drain feature has a T-shaped profile.

6. The FinFET device of claim 1 wherein the semiconductor substrate and the fin structure include silicon.

7. A FinFET device comprising:

a fin structure of semiconductor material disposed over a semiconductor substrate;

a gate structure disposed on a portion of the fin structure, the gate structure traversing the fin structure, the gate structure separating a source region and a drain region of the fin structure, wherein the source and drain region define a channel therebetween;

a set of seal spacers disposed on sidewalls of the gate structure and traversing the fin structure; and

a source region and a drain region, wherein the source and drain region includes a strained source and drain feature respectively, the strained source and drain feature each include;

a first portion having a first width and a first depth, wherein the first portion has at least a portion in direct contact with the seal spacers has a first edge extending to a depth within the fin structure that is below the gate structure, the edge being substantially coplanar with an outer edge of one of the seal spacers from the set of seal spacers to the depth within the fin structure, and wherein the first edge directly interfaces the fin structure of semiconductor material; and

a second portion disposed below the first portion, the second portion having a second width, a second depth, and a second edge expending to the second depth within the fin structure, wherein the first width is greater than the second width and wherein the second edge directly interfaces the fin structure of semiconductor material, and wherein the strained source and drain feature being formed entirely of the same material.

8. The FinFET device of claim 7 wherein the strained source and drain feature has a T-shaped profile.

9. The FinFET device of claim 7 wherein the first depth is less than the second depth.

10. The FinFET device of claim 7 wherein a distance between the channel and the source and drain feature is approximately equal to a thickness of one of the seal spacers.

11. The FinFET device of claim 7 wherein the strained source and drain feature includes silicon germanium.

12. The FinFET device of claim 7 wherein the semiconductor substrate and the fin structure include silicon.

13. A semiconductor device, comprising:

a fin structure of semiconductor material disposed over the semiconductor substrate;

a first gate structure disposed on and traversing a portion of the fin structure;

a second gate structure disposed on and traversing another portion of the fin structure;

a source/drain region interposing the first and second gate structures, wherein the source/drain region includes a contiguous region comprising a material and having;

a first portion having a first width defined by a first and second edge; and

a second portion disposed below the first portion having a second width defined by a third and fourth edge, wherein the first width is greater than the second width, wherein each of the first, second, third and fourth edges directly interfaces with the fin structure.

14. The semiconductor device of claim 13, wherein the first edge is substantially collinear with an edge of a first spacer formed on a sidewall of the first gate structure.

15. The semiconductor device of claim 14, wherein the second edge is substantially collinear with an edge of a second spacer formed on a sidewall of the second gate structure.

16. The semiconductor device of claim 13, wherein the first portion has a first depth and the second portion has a second depth, and wherein the first depth is less than the second depth.

17. The semiconductor device of claim 13, wherein the material of the contiguous region is silicon germanium.

18. The semiconductor device of claim 13, wherein the material of the contiguous region is silicon.

19. The semiconductor device of claim 18, wherein the silicon is epitaxial silicon.