Buried gate transistor

• US 8,796,762 B2
• Filed: 10/25/2012
• Issued: 08/05/2014
• Est. Priority Date: 07/06/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Lindsay, Richard, Hierlemann, Matthias
• Primary Examiner(s): PARKER, ALLEN L
• Application Number:
  US13/660,956
• Publication Number:
  US 20130049090A1
• Time in Patent Office: 649 Days
• Field of Search: 257330-334, 257/E29.26, 257/E21.384, 257/E21.419, 257/E21.428, 438/199, 438/259
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66613 with a gate recessing step, e.g. using local oxidation making recessed gate LDMOS transistors H01L29/66704
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7834 : with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H10B 12/053 : the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.

Claims

1. A semiconductor device having a buried gate transistor, the semiconductor device comprising:

a semiconductor body that includes a first active region surrounded by a trench isolation region;

a recess in a surface of the first active region, the recess having a bottom surface and vertical sidewalls;

a dielectric layer continuously and conformal lining an entire length of the bottom surface and the vertical sidewalls of the recess;

an electrode material filling the recess, wherein an upper portion of the electrode material extends above an uppermost surface of the first active region;

source/drain regions disposed in the first active region, the source/drain regions physically contacting a majority but not all of a length of the dielectric layer lining the vertical sidewalls of the recess;

a continuous doped channel region between the source/drain regions, the continuous doped channel region having a higher doping concentration along the bottom surface and a lower doping concentration along the vertical sidewalls; and

localized halo regions disposed in the first active region directly under the vertical sidewalls but not in a central portion of the continuous doped channel region.

2. The semiconductor device of claim 1, wherein the electrode material comprises a material selected from the group consisting of polysilicon, a metal, and combinations thereof.

3. The semiconductor device of claim 1, wherein the electrode material has a substantially uniform thickness within the first active region.

4. The semiconductor device of claim 1, wherein the dielectric layer comprises a material selected from the group consisting of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, and nitrided compounds thereof.

5. The semiconductor device of claim 1, further comprising:

a first source/drain region disposed in the first active region;

a second source/drain region disposed in the first active region, the second source/drain region separated from the first source/drain region by the recess; and

the continuous doped channel region beneath the recess adjacent the first and second source/drain regions.

6. The semiconductor device of claim 5, further comprising:

a first epitaxial semiconductor region above the first source/drain region; and

a second epitaxial semiconductor region above the second source/drain region.

7. The semiconductor device of claim 5, further comprising silicide regions, wherein the silicide regions comprise:

a first silicide region above the first source/drain region; and

a second silicide region above the second source/drain region.

8. The semiconductor device of claim 7, wherein the semiconductor device comprises an n-channel transistor disposed in the first active region and a p-channel transistor disposed in a second active region, wherein the electrode material serves as a gate electrode for both the n-channel transistor and the p-channel transistor.

9. The semiconductor device of claim 1, further comprising:

a dynamic random access memory cell, wherein the electrode material is electrically coupled to a word line; and

a capacitor coupled to the first active region of the semiconductor body.

10. The semiconductor device of claim 9, wherein the capacitor comprises a stack capacitor.

11. The semiconductor device of claim 1, further comprising a spacer region physically contacting the electrode material along a first part of vertical sidewalls of the upper portion of the electrode material, wherein the spacer region has a top surface which tapers down in a direction away from the vertical sidewalls.

12. The semiconductor device of claim 11, further comprising:

an insulating layer disposed between the spacer region and a first portion of the uppermost surface of the first active region, sidewalls of the insulating layer being disposed on a second part of the vertical sidewalls of the upper portion of the electrode material; and

a silicide region disposed on a second portion of the upper surface of the first active region, the silicide region being laterally spaced from the electrode material by the spacer region.

13. The semiconductor device of claim 1, further comprising a second active region separated from the first active region by the trench isolation region, wherein the recess extends from the first active region across the trench isolation region to the second active region.

14. A semiconductor device having a buried gate transistor, the semiconductor device comprising:

a first active region surrounded by a trench isolation region;

a recess in a surface of the first active region, the recess having a bottom surface and vertical sidewalls;

a dielectric layer lining the bottom surface and the vertical sidewalls;

an electrode material filling the recess;

heavily doped source/drain regions disposed in the first active region, the heavily doped source/drain regions physically contacting a portion of the vertical sidewalls of the recess and the electrode material disposed between the source region and the drain region; and

a continuous doped channel region disposed between the heavily doped source/drain regions and contacting the heavily doped source/drain regions, the continuous doped channel region having a higher doping concentration along the bottom surface and a lower doping concentration along the vertical sidewalls, wherein the electrode material filling the recess, the heavily doped source/drain regions and the continuous doped channel region form part of the buried gate transistor.

15. The semiconductor device of claim 14, further comprising a second active region separated from the first active region by the trench isolation region, wherein the recess extends from the first active region across the trench isolation region to the second active region.

16. The semiconductor device of claim 15, wherein the first active region comprises a pMOS buried gate transistor and wherein the second active region comprises an nMOS buried gate transistor.

17. The semiconductor device of claim 14, further comprising a spacer that physically contacts sidewalls of an upper portion of the electrode material, wherein a top surface of the spacer tapers down in a direction away from the sidewalls of the upper portion of the electrode material.

18. The semiconductor device of claim 17, further comprising an insulating layer disposed between the spacer and an uppermost surface of the first active region, wherein the spacer is entirely above an uppermost surface of the insulating layer.

19. The semiconductor device of claim 14, wherein an upper portion of the electrode material extends above an upper surface of the first active region.

20. The semiconductor device of claim 14, further comprising localized halo regions disposed in the first active region directly under the vertical sidewalls but not in a central portion of the continuous doped channel region.

21. The semiconductor device of claim 14, wherein a portion of the continuous doped channel region is disposed along a portion of the vertical sidewalls.

22. A semiconductor device having a buried gate transistor, the semiconductor device comprising:

a first active region surrounded by a trench isolation region;

a recess in a surface of the first active region, the recess having a bottom surface and vertical sidewalls;

a dielectric layer lining the bottom surface and the vertical sidewalls;

an electrode material filling the recess;

heavily doped source/drain regions disposed in the first active region, the heavily doped source/drain regions physically contacting the vertical sidewalls of the recess and the electrode material disposed between the source region and the drain region;

a continuous doped channel region disposed between the heavily doped source/drain regions and contacting the heavily doped source/drain regions, the continuous doped channel region having a higher doping concentration along the bottom surface and a lower doping concentration along the vertical sidewalls; and

localized halo regions disposed in the first active region directly under the vertical sidewalls but not in a central portion of the continuous doped channel region, wherein a first portion of the localized halo regions overlap with a portion of the heavily doped source/drain regions and a second portion of the localized halo regions is disposed within the continuous doped channel region.

23. The semiconductor device of claim 22, wherein a portion of the localized halo regions is disposed along the vertical sidewalls.