Semiconductor device with electrically floating body

• US 8,796,770 B2
• Filed: 07/23/2013
• Issued: 08/05/2014
• Est. Priority Date: 01/26/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Okhonin, Serguei
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US13/948,943
• Publication Number:
  US 20130308379A1
• Time in Patent Office: 378 Days
• Field of Search: 257/347, 257/348, 365/182, 438/158, 438/149, 438/517
• US Class Current: 257/347
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region, and a gate is disposed over a first portion of the body region. The device includes a source region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the source region from the first portion. The device includes a drain region adjoining a third portion of the body region, the third portion adjacent the first portion and separating the drain region from the first portion.

Claims

1. An integrated circuit device comprising:

a memory cell including a transistor, the transistor comprising;

a body region configured to be electrically floating;

a gate disposed over a first portion of the body region;

a source region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the source region from the first portion; and

a drain region adjoining a third portion of the body region, the third portion adjacent the first portion and separating the drain region from the first portion;

wherein the memory cell is configured to store a first data state representative of a first charge in the first portion of the body region;

wherein the memory cell is configured to store a second data state representative of a second charge in the first portion of the body region; and

data write circuitry coupled to the memory cell, the data write circuitry configured to apply first write control signals to the memory cell to write the first data state to the memory cell and second write control signals to the memory cell to write the second data state to the memory cell, wherein, in response to first write control signals, the electrically floating body transistor generates a first source current which substantially provides the first charge in the first portion of the body region.

2. The integrated circuit device of claim 1, wherein the first write control signals cause the first source current.

3. The integrated circuit device of claim 1, wherein the first write control signals include a signal applied to the gate and a signal applied to the source region, wherein the signal applied to the gate includes a first voltage having a first amplitude and a second voltage having a second amplitude.

4. The integrated circuit device of claim 1, wherein the first write control signals include a signal applied to the gate and a signal applied to the drain region, wherein the signal applied to the gate includes a first voltage having a first amplitude and a second voltage having a second amplitude.

5. The integrated circuit device of claim 1, wherein the first write control signals cause a potential difference between the source region and the drain region.

6. The integrated circuit device of claim 5, wherein the first write control signals include a signal applied to the gate, wherein the signal applied to the gate includes a first voltage having a first amplitude and a second voltage having a second amplitude.

7. The integrated circuit device of claim 1, wherein the first write control signals include a signal applied to the gate, a signal applied to the source region, and a signal applied to the drain region to cause the first source current, wherein:

the signal applied to the source region includes a first voltage having a first amplitude;

the signal applied to the drain region includes a second voltage having a second amplitude; and

the signal applied to the gate includes a third voltage having a third amplitude and a fourth voltage having a fourth amplitude.

8. The integrated circuit device of claim 1, wherein the first write control signals cause a first potential difference between the source region and the drain region and include a signal applied to the gate that includes a first voltage, wherein the first write control signals cause an accumulation of minority carriers in the first portion of the body region.

9. The integrated circuit device of claim 8, wherein the minority carriers accumulate at a surface region of the first portion of body region that is disposed near a gate dielectric, which is disposed between the gate and the first portion of the body region.

10. The integrated circuit device of claim 8, wherein the minority carriers accumulate at a surface region of the first portion of the body region, wherein the surface region is disconnected from the source region by the second portion of the body region.

11. The integrated circuit device of claim 8, wherein the minority carriers accumulate at a surface region of the first portion of the body region, wherein the surface region is disconnected from the drain region by the third portion of the body region.

12. The integrated circuit device of claim 8, wherein the first write control signals cause the first source current in the body region as a result of impact ionization induced by the minority carriers.

13. The integrated circuit device of claim 8, wherein the signal applied to the gate temporally changes to a second voltage that causes an accumulation of majority carriers in the first portion of the body region, wherein the majority carriers result in the first data state.

14. The integrated circuit device of claim 8, wherein the second write control signals cause a second potential difference between the source region and the drain region and include a signal applied to the gate that includes the first voltage, wherein the second write control signals prevent the first data state from being written into the first portion of the body transistor.

15. The integrated circuit device of claim 8, wherein the second potential difference is relatively less than the first potential difference.

16. The integrated circuit device of claim 1, comprising data sense circuitry coupled to the memory cell and configured to sense the data state of the memory cell, wherein, in response to read control signals applied to the memory cell, the transistor generates a second source current which is representative of the data state of the memory cell, wherein the data sense circuitry determines the data state of the memory cell at least substantially based on the second source current.

17. The integrated circuit device of claim 16, wherein the read control signals include signals applied to one or more of the gate, source region, and drain region to cause the second source current which is representative of the data state of the memory cell.

18. The integrated circuit device of claim 16, wherein the read control signals cause a first potential difference between the source region and the drain region.

19. The integrated circuit device of claim 18, wherein the signal applied to the gate includes a negative voltage pulse.

20. The integrated circuit device of claim 1, wherein the source region of the memory cell is connected to a source region of one or more additional memory cells in a row of memory cells in the integrated circuit device.