Borderless contact structure employing dual etch stop layers

• US 8,796,783 B2
• Filed: 02/26/2013
• Issued: 08/05/2014
• Est. Priority Date: 04/28/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Fan, Su C., Horak, David V., Koburger, Charles W., Ponoth, Shom, Yang, Chih-Chao
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): THOMAS, TONIAE M
• Application Number:
  US13/777,410
• Publication Number:
  US 20130168749A1
• Time in Patent Office: 525 Days
• Field of Search: 257/382, 257/637, 257/E29.116
• US Class Current: 257/382
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Each gate structure formed on the substrate includes a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric. A second etch stop layer is formed over the gate structures, gate spacers, and source and drain regions. A first contact-level dielectric layer and a second contact-level dielectric layer are formed over the second etch stop layer. Gate contact via holes extending at least to the top surface of the gate cap dielectrics are formed. Source/drain contact via holes extending to the interface between the first and second contact-level dielectric layers are subsequently formed. The various contact via holes are vertically extended by simultaneously etching exposed gate cap dielectrics and exposed portions of the first contact-level dielectric layer, then by simultaneously etching the first and second etch stop layers. Source/drain contact vias self-aligned to the outer surfaces gate spacers are thereby formed.

Claims

1. A semiconductor structure comprising:

at least one gate structure located on a semiconductor substrate, wherein each of said at least one gate structure includes, from bottom to top, a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric;

a second etch stop layer located on said at least one gate structure;

a first contact-level dielectric layer and a second contact-level dielectric layer located over said second etch stop layer;

at least one gate contact via structure embedded in said first and second contact-level dielectric layers, wherein each of said at least one gate contact via structure extends through said first and second contact-level dielectric layers, said second etch stop layer, one of said at least one gate cap dielectric, and one of said at least one first etch stop layer; and

at least one source/drain contact via structure embedded in said first and second contact-level dielectric layers, wherein each of said at least one source/drain contact via structure extends through said first and second contact-level dielectric layers and said second etch stop layer.

2. The semiconductor structure of claim 1, further comprising at least one gate spacer located on said semiconductor substrate, wherein each of said at least one gate spacer laterally surrounds one of said at least one gate structure.

3. The semiconductor structure of claim 2, wherein said second etch stop layer is located directly on said at least one gate spacer.

4. The semiconductor structure of claim 2, wherein said at least one gate spacer comprises a different material than said at least one first etch stop layer and said second etch stop layer.

5. The semiconductor structure of claim 2, wherein a portion of said at least one source/drain contact via structure contacts an outer surface of said at least one gate spacer.

6. The semiconductor structure of claim 2, wherein one of said at least one gate spacer laterally surrounds one of said at least one gate structure, said one of said at least one gate structure in which a gate conductor, a first etch stop layer, and a gate cap dielectric have a same width.

7. The semiconductor structure of claim 2, wherein one of said at least one gate contact via structure contacts an inner sidewall of one of said at least one gate spacer.

8. The semiconductor structure of claim 2, wherein one of said at least one source/drain contact via structure contacts an outer sidewall of one of said at least one gate spacer.

9. The semiconductor structure of claim 1, wherein said at least one first etch stop comprises a material that is different from a material of said at least one gate cap dielectric and said first contact-level dielectric material layer.

10. The semiconductor structure of claim 9, wherein said second etch stop layer comprises a material that is different from said material of said at least one gate cap dielectric and said first contact-level dielectric material layer.

11. The semiconductor structure of claim 1, each of said at least one first etch stop layer and said second etch stop layer comprises a material that is different from a material of said at least one gate cap dielectric and said first contact-level dielectric material layer.

12. The semiconductor structure of claim 11, wherein each of said at least one first etch stop layer and said second etch stop layer is selected from HfO₂, Y₂O₃, and Al₂O₃.

13. The semiconductor structure of claim 11, wherein said at least one first etch stop layer and said second etch stop layer comprise a same dielectric metal oxide.

14. The semiconductor structure of claim 1, wherein each of said at least one first etch stop layer and said second etch stop layer comprises a material selected from silicon oxide, silicon nitride, and a dielectric metal oxide.

15. The semiconductor structure of claim 14, wherein each of said at least one first etch stop layer and said second etch stop layer comprises a dielectric metal oxide.

16. The semiconductor structure of claim 1, wherein said at least one gate cap dielectric and said first contact-level dielectric layer comprise a first dielectric material, and said second contact-level dielectric layer comprises a second dielectric material different from said first dielectric material.

17. The semiconductor structure of claim 1, wherein said at least one first etch stop layer includes a conductive metallic compound.

18. The semiconductor structure of claim 1, wherein each of said at least one source/drain contact via structure contacts a source/drain region on said semiconductor substrate.

19. The semiconductor structure of claim 18, wherein said second etch stop layer contacts at least one source/drain region.

20. The semiconductor structure of claim 1, wherein each of said at least one source/drain contact via structure contacts a raised source/drain region located on a top surface of said semiconductor substrate.