Low-dropout regulator overshoot control

• US 8,797,008 B2
• Filed: 01/06/2012
• Issued: 08/05/2014
• Est. Priority Date: 01/06/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Devegowda, Sachin
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): Quddus, Nusrat
• Application Number:
  US13/344,890
• Publication Number:
  US 20130176007A1
• Time in Patent Office: 942 Days
• Field of Search: 323273-281
• US Class Current: 323/274
• CPC Class Codes: G05F 1/573 with overcurrent detector

Abstract

Representative implementations of devices and techniques control regulator output overshoot. An offset signal is provided to a component of the regulator during at least a portion of the regulator start-up.

Claims

1. A circuit arranged to control a voltage overshoot at a voltage regulator, comprising:

a power source arranged to produce an offset signal;

a switch arranged to combine the offset signal from the power source to a signal at an input of the voltage regulator in response to an enable signal;

a timing component arranged to send the enable signal to the switch during a start-up of the voltage regulator; and

a voltage regulation loop having a loop gain, a duration for the loop gain to reach a preset threshold being less than a time duration for an output of the voltage regulator to reach a nominal operating voltage.

2. The circuit of claim 1, wherein the timing component is arranged to cease the enable signal to the switch when at least two differential inputs to the voltage regulator have substantially equal currents.

3. The circuit of claim 1, wherein the offset signal comprises at least one of an offset voltage and an offset current.

4. The circuit of claim 1, wherein the switch is arranged to combine the offset signal with a feedback voltage at a voltage regulation loop of the voltage regulator.

5. The circuit of claim 1, wherein the switch is arranged to combine the offset signal with a reference voltage received by the voltage regulator.

6. The circuit of claim 1, wherein the circuit is arranged to offset a voltage at an output of the voltage regulator.

7. A system, comprising:

a low drop out voltage regulator, including;

an error amplifier having a first input connected to a reference voltage and a second input connected to a feedback voltage, an output of the voltage regulator being based on the reference voltage and the feedback voltage; and

a voltage regulation loop coupled to the second input of the error amplifier and arranged to provide the feedback voltage; and

an offset circuit arranged to add an offset voltage to the feedback voltage during at least a portion of a start-up of the voltage regulator,

wherein a time duration for a loop gain of the voltage regulation loop to reach a preset threshold is less than a time duration for an output of the voltage regulator to reach a nominal operating voltage.

8. The system of claim 7, further comprising a current limiter arranged to determine a current flow through the voltage regulator during at least a portion of the start-up of the voltage regulator and to determine when the offset voltage is added to the feedback voltage.

9. The system of claim 8, wherein the current limiter is arranged to enable the addition of the offset voltage to the feedback voltage upon commencement of the start-up of the voltage regulator and to disable the addition of the offset voltage to the feedback voltage when the feedback voltage reaches a preset minimum common mode potential.

10. The system of claim 8, wherein the current limiter is arranged to enable the addition of the offset voltage to the feedback voltage upon commencement of the start-up of the voltage regulator and to disable the addition of the offset voltage to the feedback voltage when the loop gain of the voltage regulation loop reaches a the preset threshold.

11. A method of controlling a voltage output of a voltage regulator, comprising:

charging a voltage regulation loop during a start-up of the voltage regulator;

adding an offset to a voltage at the voltage regulation loop during charging of the voltage regulation loop;

removing the offset when the voltage regulation loop reaches a preset threshold loop gain; and

reducing a time duration for the voltage regulation loop to reach a preset minimum loop gain based on adding the offset to the voltage at the voltage regulation loop.

12. The method of claim 11, further comprising charging an error amplifier of the voltage regulator during start-up of the voltage regulator and adding the offset voltage to a voltage at an input of the error amplifier while charging the error amplifier.

13. The method of claim 11, further comprising charging the voltage regulator via a pass through device, wherein the pass through device is current limited during at least a portion of the start-up.

14. The method of claim 11, further comprising charging the output of the voltage regulator to a preset nominal value after removing the offset.

15. The method of claim 11, further comprising reducing a time duration for the voltage regulation loop to reach a preset maximum loop gain based on adding the offset to the voltage at the voltage regulation loop.

16. The method of claim 11, further comprising increasing a time duration for an output of the voltage regulator to reach a preset nominal operating voltage based on adding the offset to the voltage at the voltage regulation loop.

17. The method of claim 11, wherein an instantaneous value of the output of the voltage regulator is reduced based on adding the offset to the voltage at the voltage regulation loop.

18. The method of claim 11, wherein a time duration for the voltage regulation loop to reach a preset minimum loop gain and a time duration for the voltage regulation loop to reach a preset maximum loop gain are less than a time duration for an output of the voltage regulator to reach a preset nominal operating voltage based on adding the offset to the voltage at the voltage regulation loop.

19. A low dropout voltage regulator, comprising:

an error amplifier having at least a first input and a second input;

a voltage regulation loop coupled to the first input of the error amplifier; and

an offset circuit arranged to provide an offset value to at least one of the first input and the second input of the error amplifier during at least a portion of a start-up of the voltage regulator,

wherein the voltage regulation loop includes a loop gain, a duration for the loop gain to reach a preset threshold being less than a time duration for an output of the voltage regulator to reach a nominal operating voltage.

20. The low dropout voltage regulator of claim 19, further comprising a reference voltage coupled to the second input of the error amplifier, and wherein the offset circuit is arranged to provide the offset value to the voltage regulation loop while a voltage at the first input of the error amplifier is less than the reference voltage.

21. The low dropout voltage regulator of claim 19, wherein the offset circuit is arranged to combine the offset value to the reference voltage at the second input of the error amplifier while a voltage at the first input of the error amplifier is less than a voltage at the second input of the error amplifier.

22. The low dropout voltage regulator of claim 19, wherein the offset circuit is arranged to provide the offset value to the at least one of the first input and the second input of the error amplifier until the voltage regulation loop reaches a preset threshold loop gain.