Hybrid H-bridge and CML driver

• US 8,797,064 B1
• Filed: 01/10/2013
• Issued: 08/05/2014
• Est. Priority Date: 09/10/2012
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Ho, Vinh, Jayaram, Magathi, Lin, Allan
• Primary Examiner(s): Hammond, Crystal L
• Application Number:
  US13/738,265
• Time in Patent Office: 572 Days
• Field of Search: None
• US Class Current: 326/86
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H04L 5/22 using time-division multiplexing

Abstract

In one embodiment, a hybrid output buffer having both an H-bridge mode and a CML mode of operation includes a plurality of transistor switches arranged between an upper rail and a bottom rail. A first pair of the transistor switches couples between the upper rail and respective output nodes. A pair of resistors couples between the output nodes and a central node. During H-bridge mode, the hybrid output buffer controls a potential of the upper rail responsive to a feedback signal proportional to a difference between a potential of the central node and a common-mode voltage.

Claims

1. A hybrid circuit comprising:

a pair of resistors coupled through a central node;

a mode control circuit configured to charge the central node to a supply voltage in a current mode logic (CML) mode of operation and to allow the central node to float in an H-bridge mode of operation;

a differential amplifier configured to compare a potential of the central node to a common-mode voltage to provide a feedback signal; and

a first PMOS transistor having its gate driven by the feedback signal, the first PMOS transistor having it source coupled to the supply voltage and a drain coupled to an upper rail for the hybrid circuit.

2. The hybrid circuit of claim 1, further comprising:

a current source configured to source a bias current.

3. The hybrid circuit of claim 2, further comprising:

a second PMOS transistor having a source coupled to the upper rail and a drain coupled to a first one of the resistors; and

a first NMOS transistor having a drain coupled to the drain of the second PMOS transistor and having a source coupled to a bottom rail, wherein the current source couples between the bottom rail and ground.

4. The hybrid circuit of claim 3, further comprising:

a third PMOS transistor having a source coupled to the upper rail and a drain coupled to a second one of the resistors; and

a second NMOS transistor having a drain coupled to the drain of the second PMOS transistor and having a source coupled to the bottom rail.

5. The hybrid circuit of claim 4, further comprising:

a first multiplexer configured to select between a first input voltage and the power supply voltage to provide an output signal for driving a gate of the second PMOS transistor; and

a second multiplexer configured to select between the first input voltage and ground to provide an output signal for driving a gate of the first NMOS transistor.

6. The hybrid circuit of claim 5, further comprising:

a third multiplexer configured to select between a second input voltage and the power supply voltage to provide an output signal for driving a gate of the third PMOS transistor; and

a fourth multiplexer configured to select between the second input voltage and ground to provide an output signal for driving a gate of the second NMOS transistor, wherein a differential input voltage for the hybrid circuit equals a difference between the second input voltage and the first input voltage.

7. The hybrid circuit of claim 6, wherein a first output node couples to the drains of the second PMOS transistor and the first NMOS transistor, and wherein a second output node couples to the drains of the third PMOS transistor and the second NMOS transistor, and wherein a differential output voltage for the hybrid circuit equals a difference between a potential for the first node and a potential for the second node.

8. The hybrid circuit of claim 2, wherein the current source is a cascaded current mirror source comprising a pair of NMOS transistors, and wherein the hybrid circuit is incorporated into a field programmable gate array.

9. The hybrid circuit of claim 1, further comprising:

a first multiplexer configured to select between the feedback signal and the power supply voltage to provide an output signal for driving the gate of the first PMOS transistor, wherein the first multiplexer is configured to select for the feedback signal in the H-bridge mode of operation and to select for the power supply voltage in the CML mode of operation.

10. A method, comprising:

in a hybrid output buffer, receiving a mode signal having a first state and a second state;

responsive to receiving the current mode signal in the first state, charging a central node of the hybrid output buffer to a power supply potential and operating the hybrid output buffer in a current mode logic (CML) mode;

responsive to receiving the current mode signal in the second state, floating a potential of central node and operating the hybrid output buffer in an H-bridge mode; and

while operating in the H-bridge mode, controlling a potential of an upper rail for the hybrid output buffer in response to a feedback signal that is proportional to a difference between the potential of the central node and a common-mode voltage.

11. The method of claim 10, further comprising:

biasing the hybrid output buffer during operation in the H-bridge mode and during operation in the CML mode with a bias current from a current source.

12. The method of claim 11, wherein the current source comprises a cascaded current source.

13. The method of claim 10, wherein controlling the potential of the upper rail comprises driving a gate of a transistor with the feedback signal.

14. The method of claim 13, wherein driving the gate of the transistor comprises driving the gate of a PMOS transistor.

15. A circuit, comprising:

a first resistor;

a second resistor coupled to the first resistor through a central node;

a plurality of hybrid output buffers that share the first and second resistors and the central node; and

a mode control circuit configured to charge the central node to a supply voltage in a current mode logic (CML) mode of operation and to allow the central node to float in an H-bridge mode of operation.

16. The circuit of claim 15, wherein each hybrid output buffer includes a top rail and a bottom rail.

17. The circuit of claim 15, wherein each hybrid output buffer further includes a current source coupled between the bottom rail and ground, each current source configured to bias its hybrid output buffer with a bias current.

18. The circuit of claim 17, wherein each current source is a cascaded current mirror source.

19. The circuit of claim 17, wherein each hybrid output buffer is configured in the H-bridge mode to control a potential for its top rail responsive to a feedback signal proportional to a difference between a potential for the central node to a common-mode voltage.

20. The circuit of claim 19, wherein each hybrid output buffer is configured to turn on and off independently of the remaining hybrid output buffers.