Parallel test payload

• US 8,797,193 B2
• Filed: 01/29/2010
• Issued: 08/05/2014
• Est. Priority Date: 01/29/2010
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Ulichney, Robert Alan, Simske, Steven J., Gaubatz, Matthew D.
• Primary Examiner(s): NGUYEN, LINH V
• Application Number:
  US13/384,951
• Publication Number:
  US 20120281920A1
• Time in Patent Office: 1,649 Days
• Field of Search: 341/56, 341/59, 341/65, 341/67
• US Class Current: 341/67
• CPC Class Codes: G11B 20/182 using test patterns
• CPC Class Codes: G11B 2220/80 Indexing information stored in optical or magnetic or other strip attached to cassette or disc, e.g. barcodes attached to a recording medium
• CPC Class Codes: H03M 7/3093 using fixed length segments
• CPC Class Codes: H03M 7/3095 using variable length segments
• CPC Class Codes: H03M 7/40 Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
• CPC Class Codes: H04N 1/00045 using a reference pattern designed for the purpose, e.g. a test chart
• CPC Class Codes: H04N 1/32256 in halftone data

Abstract

A parallel test payload includes a bit sequence configured to be segmented into a plurality of sub-sequences having variable bit length carriers. Respective carriers are represented uniformly in each one of the plurality of sub-sequences.

Claims

1. A parallel test payload, comprising:

a bit sequence configured to be segmented into a plurality of sub-sequences having variable bit length carriers; and

each of the plurality of sub-sequences including;

respective carriers represented uniformly in a respective sub-sequence such that each of the respective carriers is present an equal number of times in the respective sub-sequence; and

a number of bits present in each of the respective carriers such that each of the respective carriers in the respective sub-sequence has a bit length that is different than a bit length of any other respective carriers in any other respective sub-sequences;

wherein the bit sequence is represented in each of the plurality of sub-sequences through the respective carriers.

4. The parallel test payload as defined in claim 1 wherein the bit sequence is embedded in an analog carrier.

5. The parallel test payload as defined in claim 4 wherein the analog carrier is selected from particles on a magnetic strip, etchings burnt into a disk, or ink printed on a substrate.

6. The parallel test payload as defined in claim 1 wherein the bit sequence after segmentation is presentable as a printable ASCII sequence.

7. The parallel test payload as defined in claim 1 wherein a maximum value of the bit length of the respective carriers is five.

10. A parallel calibration method, comprising:

generating the parallel test payload of claim 1;

embedding data of the parallel test payload onto a plurality of different carrier cells of a comprehensive carrier configuration, thereby generating a digital composite signal;

converting the digital composite signal to analog form on a data-bearing medium;

converting the analog signal to a recovered digital signal;

performing an inverse embedding process to extract recovered data of the parallel test payload from the recovered digital signal; and

generating recovery statistics by comparing the recovered data with the embedded data.

11. The method as defined in claim 10 wherein generating the parallel test payload is accomplished by:

generating the bit sequence; and

segmenting the bit sequence into the plurality of sub-sequences having the variable bit length carriers such that respective carriers are represented uniformly in each one of the plurality of sub-sequences, the segmenting including;

selecting the bit length for the respective carriers of the respective sub-sequence; and

dividing the bit sequence such that a number of bits present in each of the respective carriers of the respective sub-sequence corresponds with the selected bit length, and such that the respective carriers are represented an equal number of times in the respective sub-sequence.

12. The method as defined in claim 10, further comprising selecting two or more carrier cells from the plurality of carrier cells for deployment of a payload based upon the recovery statistics.

13. The method as defined in claim 12 wherein the generating of the recovery statistics includes:

classifying the recovered data as a carrier type;

comparing the carrier type of the recovered data with a carrier type previously assigned to the embedded data; and

from the comparison, determining at least one of recall statistics, precision statistics, or accuracy statistics.

14. The method as defined in claim 12, further comprising using a recovery rate of each of the two or more carrier cells selected to design payload redundancy for error correction.

2. A parallel test payload, comprising:

a bit sequence configured to be segmented into a plurality of sub-sequences having variable bit length carriers; and

respective carriers represented uniformly in each one of the plurality of sub-sequences;

wherein the bit sequence includes twenty four bits; and

wherein the variable bit length carriers include a three-bit length carrier, a two-bit length carrier, and a one-bit length carrier.

3. The parallel test payload as defined in claim 2 wherein eight carriers of the bit sequence are represented once when the bit sequence is segmented into a sub-sequence having the three-bit length carriers;

wherein four carriers of the bit sequence are represented three times when the bit sequence is segmented into a sub-sequence having the two-bit length carriers; and

wherein each carrier of the bit sequence is represented equally when the bit sequence is segmented into a sub-sequence having the one-bit length carriers.

8. A method for generating a parallel test payload, comprising:

generating a bit sequence; and

segmenting the bit sequence into a plurality of sub-sequences having variable bit length carriers such that respective carriers are represented uniformly in each one of the plurality of sub-sequences and such that the bit sequence is represented in each of the plurality of sub-sequences through the respective carriers, the segmenting including;

selecting a bit length for the respective carriers of a respective sub-sequence, the bit length for the respective carriers of the respective sub-sequence being different from a bit length for any other respective carriers in any other respective sub-sequences; and

dividing the bit sequence such that a number of bits present in each of the respective carriers of the respective sub-sequence corresponds with the selected bit length, and such that the respective carriers are represented an equal number of times in the respective sub-sequence.

9. The method as defined in claim 8, further comprising embedding the parallel test payload into at least one analog carrier on a data-bearing medium.

15. A method for generating a parallel test payload, comprising:

generating a bit sequence; and

segmenting the bit sequence into a plurality of sub-sequences having variable bit length carriers such that respective carriers are represented uniformly in each one of the plurality of sub-sequences;

wherein the bit sequence includes twenty four bits; and

wherein the variable bit length carriers include a three-bit length carrier, a two-bit length carrier, and a one-bit length carrier.

16. The method as defined in claim 15 wherein eight carriers of the bit sequence are represented once when the bit sequence is segmented into a sub-sequences having the three-bit length carriers;

wherein four carriers of the bit sequence are represented three times when the bit sequence is segmented into a sub-sequences having the two-bit length carriers; and

wherein each carrier of the bit sequence is represented equally when the bit sequence is segmented into a sub-sequences having the one-bit length carriers.