Low-power area-efficient SAR ADC using dual capacitor arrays

• US 8,797,204 B2
• Filed: 08/31/2010
• Issued: 08/05/2014
• Est. Priority Date: 09/01/2009
• Status: Active Grant

• Current Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Original Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Inventors: Yoon, Euisik, Chang, Sun-Il
• Primary Examiner(s): NGUYEN, LINH V
• Application Number:
  US13/393,685
• Publication Number:
  US 20120218137A1
• Time in Patent Office: 1,435 Days
• Field of Search: 341/118, 341/120, 341/155, 341/156, 341/144, 341/172
• US Class Current: 341/172
• CPC Class Codes: H03M 1/16 with scale factor modification, i.e. by changing the amplification between the steps H03M1/141 takes precedence
• CPC Class Codes: H03M 1/442 using switched capacitors
• CPC Class Codes: H03M 1/466 using switched capacitors
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

An analog to digital converter that comprises a successive approximation register (SAR) having an n bit binary output, a first capacitor array connected to receive some of the bits of the binary output, a second capacitor array connected to receive the remaining bits of the binary output, and a comparator including an output connected to the SAR. The first and second capacitor arrays each have an analog output indicative of the charge stored by capacitors of that array. The comparator includes a pair of inputs, one of which is connected to the analog output of the first capacitor array and the other of which is connected to the analog output of the second capacitor array.

Claims

1. An analog to digital converter, comprising:

a successive approximation register (SAR) having an n-bit binary output;

a first capacitor array connected to receive some of the bits of the binary output;

a second capacitor array connected to receive the remaining bits of the binary output, wherein the first and second capacitor arrays each have an analog output indicative of the charge stored by capacitors of that array, the first capacitor array uses a first reference voltage level, and the second capacitor array uses a second reference voltage equal to the first reference voltage divided by 2^n/2; and

a comparator including an output connected to the SAR and including a pair of inputs, one of which is connected to the analog output of the first capacitor array and the other of which is connected to the analog output of the second capacitor array;

wherein the analog to digital converter includes an analog voltage input that receives an inputted analog voltage to be converted to digital form, and wherein the first capacitor array includes a switch that interconnects the analog voltage input to the capacitors of the first capacitor array such that, when connected to the analog voltage input by the switch, the first capacitor array samples the inputted analog voltage.

2. An analog to digital converter as defined in claim 1, wherein n is a positive, even integer and wherein each capacitor array is connected to receive n/2 of the bits of the binary output.

3. An analog to digital converter as defined in claim 2, wherein the first capacitor array is connected to the SAR to receive the least significant bits of the binary output and the second capacitor array is connected to the SAR to receive the most significant bits of the binary output, and wherein the pair of inputs of the comparator include an inverting input connected to the analog output of the first capacitor array and a non-inverting input connected to the analog output of the second capacitor array.

4. An analog to digital converter as defined in claim 2, wherein each capacitor array includes n/2 binary weighted capacitors, and wherein the total capacitance of the binary weighted capacitors in each array is 2^(n/2).

5. An analog to digital converter, comprising:

a successive approximation register (SAR) having an n-bit binary output that includes a most significant bit (MSB) and a least significant bit (LSB);

a comparator; and

a plurality of n binary weighted capacitors each of which is associated with one of the bits of the binary output, the binary weighted capacitors including a first capacitor having a unit capacitance C associated with the LSB and one or more other capacitors each of which is associated with one of the other bits of the binary output and each of which has a capacitance value equal to 2ⁱ×

C where i and n are integers and 0≦

i≦

n/2;

wherein the binary weighted capacitors are grouped into first and second capacitor arrays and the first capacitor array uses a first reference voltage whereas the second capacitor array uses a second reference voltage equal to the first reference voltage divided by 2^n/2 and

the analog to digital converter includes an analog voltage input that receives an inputted analog voltage to be converted to digital form, and further includes a switch that interconnects the analog voltage input to a group of the capacitors associated with the LSB such that, when connected to the analog voltage input by the switch, the capacitors of the group associated with the LSB each receive the inputted analog voltage.

6. An analog to digital converter as defined in claim 5, wherein each of the binary weighted capacitors comprises a single capacitor.

7. An analog to digital converter as defined in claim 5, wherein at least one of the binary weighted capacitors comprises a plurality of individual capacitors connected together to provide a capacitance equal to 2ⁱ×

C.

8. An analog to digital converter as defined in claim 5, wherein the bits of the binary output of the SAR are each connected to their associated binary weighted capacitors such that, during one or more successive approximation iterations, the bits of the binary output control the storage of charge on their associated binary weighted capacitors.

9. An analog to digital converter as defined in claim 5, wherein n is a positive, even integer and wherein the binary weighted capacitors are grouped into first and second capacitor arrays, each of said arrays containing n/2 of the binary weighted capacitors and wherein each of the binary weighted capacitors contained in each array has a capacitance that is different than the capacitance of the other binary weighted capacitors in that array.

10. An analog to digital converter as defined in claim 9, wherein the first capacitor array is connected to an inverting input of the comparator and the second capacitor array is connected to an non-inverting input of the comparator.

11. An analog to digital converter, comprising:

an analog voltage input that receives an inputted analog voltage to be converted to digital form;

a successive approximation register (SAR) having an n-bit binary output including a most significant bit (MSB) and a least significant bit (LSB);

a comparator having inverting and non-inverting inputs and an output that is connected to the SAR;

a first capacitor array comprising an upper digital to analog converter (DAC) having an m-bit binary input, wherein m and n are positive integers with m<

n, and wherein each of the m-bits is connected to a corresponding bit of the SAR'"'"'s binary output including one of the m-bits being connected to the LSB;

a second capacitor array comprising a lower DAC having an n-m bit binary input, wherein each of the n-m bits is connected to a corresponding bit of the SAR'"'"'s binary output including one of the n-m bits being connected to the MSB, wherein the first capacitor array uses a first reference voltage level and the second capacitor array uses a second reference voltage equal to the first reference voltage divided by 2^n/2; and

a switch selectively interconnecting the first capacitor array to either the analog voltage input or a reference voltage;

wherein the first capacitor array comprises a plurality of switched capacitors, each of which are connectable via the switch to either the analog voltage input or the reference voltage;

wherein the first and second capacitor arrays each have an analog output that is connected to a different one of the inputs of the comparator.

12. An analog to digital converter as defined in claim 11, wherein the first capacitor array is connected to the SAR to receive the least significant bits of the binary output and the second capacitor array is connected to the SAR to receive the most significant bits of the binary output, and wherein the analog output of the first capacitor array is connected to the inverting input of the comparator and the analog input of the second capacitor array is connected to the non-inverting input of the comparator.

13. An analog to digital converter as defined in claim 11, wherein n is an even integer and m=n/2.

14. An analog to digital converter as defined in claim 13, wherein the SAR, comparator, and capacitor arrays together comprise an integrated circuit formed on a chip, and wherein the area on the chip occupied by the capacitor arrays is less than three times the total area on the chip that is occupied by the comparator and SAR.