Semiconductor device

• US 8,797,785 B2
• Filed: 11/10/2011
• Issued: 08/05/2014
• Est. Priority Date: 11/12/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Saito, Toshihiko
• Primary Examiner(s): Le, Vu
• Assistant Examiner(s): Yang, Han
• Application Number:
  US13/293,173
• Publication Number:
  US 20120120715A1
• Time in Patent Office: 999 Days
• Field of Search: 365/149, 365/145, 365/174
• US Class Current: 365/149
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

Provided is a memory device in which memory capacity per unit area is increased without making the manufacturing process complicated. The memory device includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. Each of the plurality of memory cells includes a switching element and a capacitor including a first electrode and a second electrode. In at least one of the plurality of memory cells, in accordance with a potential applied to one of the plurality of word lines, the switching element controls a connection between one of the plurality of bit lines and the first electrode, and the second electrode is connected to another one of the plurality of word lines.

Claims

1. A semiconductor device comprising:

a first memory cell comprising a first switching element and a first capacitor;

a second memory cell comprising a second switching element and a second capacitor;

a first word line;

a second word line;

a first bit line; and

a second bit line,

wherein the first switching element is configured to control an electrical connection between the first bit line and a first electrode of the first capacitor in accordance with a potential applied to the first word line,

wherein the second switching element is configured to control an electrical connection between the second bit line and a first electrode of the second capacitor in accordance with a potential applied to the second word line,

wherein a second electrode of the second capacitor is electrically connected to the first word line,

wherein the first memory cell and the second memory cell are stacked, and

wherein the second memory cell is over the first memory cell.

2. The semiconductor device according to claim 1, wherein the first switching element is a transistor comprising a semiconductor film comprising an oxide semiconductor.

3. The semiconductor device according to claim 2, wherein the oxide semiconductor comprises In, Ga and Zn.

4. The semiconductor device according to claim 2, wherein a hydrogen concentration of the semiconductor film is lower than 1×

10¹⁹/cm³.

5. A semiconductor device comprising:

a plurality of first memory cells;

a plurality of first word lines;

a plurality of first bit lines;

a plurality of second memory cells;

a plurality of second word lines;

a plurality of second bit lines; and

a capacitor line,

wherein each of the plurality of first memory cells comprises a first switching element and a first capacitor,

wherein each of the plurality of second memory cells comprises a second switching element and a second capacitor,

wherein in at least one of the plurality of first memory cells, in accordance with a potential applied to one of the plurality of first word lines, the first switching element is configured to control an electrical connection between one of the plurality of first bit lines and a first electrode of the first capacitor,

wherein a second electrode of the first capacitor is electrically connected to the capacitor line,

wherein in at least one of the plurality of second memory cells, in accordance with a potential applied to one of the plurality of second word lines, the second switching element is configured to control an electrical connection between one of the plurality of second bit lines and a first electrode of the second capacitor,

wherein a second electrode of the second capacitor is electrically connected to one of the plurality of first word lines,

wherein the plurality of first memory cells and the plurality of second memory cells are stacked,

wherein the plurality of second memory cells is over the plurality of first memory cells,

wherein the plurality of first word lines is over the capacitor line, and

wherein the plurality of second word lines is over the plurality of first word lines.

6. The semiconductor device according to claim 5, wherein the first switching element is a transistor comprising a semiconductor film comprising an oxide semiconductor.

7. The semiconductor device according to claim 6, wherein the oxide semiconductor comprises In, Ga and Zn.

8. The semiconductor device according to claim 6, wherein a hydrogen concentration of the semiconductor film is lower than 1×

10¹⁹/cm³.

9. A semiconductor device comprising:

a first memory cell comprising a first transistor and a first capacitor;

a second memory cell comprising a second transistor and a second capacitor;

a first word line;

a second word line;

a first bit line; and

a second bit line,

wherein one of a source and a drain of the first transistor is electrically connected to the first bit line,

wherein the other of the source and the drain of the first transistor is electrically connected to a first electrode of the first capacitor,

wherein a gate of the first transistor is electrically connected to the first word line,

wherein one of a source and a drain of the second transistor is electrically connected to the second bit line,

wherein the other of the source and the drain of the second transistor is electrically connected to a first electrode of the second capacitor,

wherein a gate of the second transistor is electrically connected to the second word line,

wherein a second electrode of the second capacitor is electrically connected to the first word line,

wherein the first memory cell and the second memory cell are stacked, and

wherein the second memory cell is over the first memory cell.

10. The semiconductor device according to claim 9, wherein the first transistor comprises a semiconductor film comprising an oxide semiconductor.

11. The semiconductor device according to claim 10, wherein the oxide semiconductor comprises In, Ga and Zn.

12. The semiconductor device according to claim 10, wherein a hydrogen concentration of the semiconductor film is lower than 1·

10¹⁹/cm³.

13. A semiconductor device comprising:

a first memory cell comprising a first transistor and a first capacitor;

a second memory cell comprising a second transistor and a second capacitor;

a first word line;

a second word line;

a first bit line; and

a second bit line,

wherein one of a source and a drain of the first transistor is electrically connected to the first bit line,

wherein the other of the source and the drain of the first transistor is electrically connected to a first electrode of the first capacitor,

wherein a gate of the first transistor is electrically connected to the first word line,

wherein one of a source and a drain of the second transistor is electrically connected to the second bit line,

wherein the other of the source and the drain of the second transistor is electrically connected to a first electrode of the second transistor,

wherein a gate of the second transistor is electrically connected to the second word line,

wherein a second electrode of the second capacitor is electrically connected to the first word line,

wherein the first transistor is over a substrate,

wherein an insulating film is over the first transistor, and

wherein the second transistor is over the insulating film.

14. The semiconductor device according to claim 13, wherein the first transistor comprises a semiconductor film comprising an oxide semiconductor.

15. The semiconductor device according to claim 14, wherein the oxide semiconductor comprises In, Ga and Zn.

16. The semiconductor device according to claim 14, wherein a hydrogen concentration of the semiconductor film is lower than 1×

10¹⁹/cm³.

17. A semiconductor device comprising:

a first memory cell comprising a first transistor and a first capacitor;

a second memory cell comprising a second transistor and a second capacitor;

a first word line;

a second word line;

a first bit line;

a second bit line; and

a capacitor line,

wherein one of a source and a drain of the first transistor is electrically connected to the first bit line,

wherein the other of the source and the drain of the first transistor is electrically connected to a first electrode of the first capacitor,

wherein a gate of the first transistor is electrically connected to the first word line,

wherein one of a source and a drain of the second transistor is electrically connected to the second bit line,

wherein the other of the source and the drain of the second transistor is electrically connected to a first electrode of the second transistor,

wherein a gate of the second transistor is electrically connected to the second word line,

wherein a second electrode of the second capacitor is electrically connected to the first word line,

wherein a second electrode of the first capacitor is electrically connected to the capacitor line,

wherein the capacitor line is over a substrate,

wherein a first insulating film is over the capacitor line,

wherein the first transistor is over the first insulating film,

wherein a second insulating film is over the first transistor, and

wherein the second transistor is over the second insulating film.

18. The semiconductor device according to claim 17, wherein the first transistor comprises a semiconductor film comprising an oxide semiconductor.

19. The semiconductor device according to claim 18, wherein the oxide semiconductor comprises In, Ga and Zn.

20. The semiconductor device according to claim 18, wherein a hydrogen concentration of the semiconductor film is lower than 1×

10¹⁹/cm³.