Apparatus and methods including source gates

• US 8,797,806 B2
• Filed: 08/15/2011
• Issued: 08/05/2014
• Est. Priority Date: 08/15/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Goda, Akira, Ahmed, Shafqat, Hasnat, Khaled, Parat, Krishna K.
• Primary Examiner(s): YOHA, CONNIE C
• Application Number:
  US13/210,194
• Publication Number:
  US 20130044549A1
• Time in Patent Office: 1,086 Days
• Field of Search: 365/185.26, 365/185.23, 365/230.06
• US Class Current: 365/185.26
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

Claims

1. An apparatus comprising:

a string of charge storage devices associated with a pillar comprising semiconductor material;

a source gate device coupled to a source and configured to control conduction between a channel of the string of charge storage devices and the source; and

a source select device coupled between the string of charge storage devices and the source gate device, the source select device configured to control conduction between the channel and the source.

2. The apparatus of claim 1, further comprising a drain select device coupled between the string of charge storage devices and a data line.

3. The apparatus of claim 1, wherein the apparatus comprises a memory device.

4. The apparatus of claim 1, wherein the apparatus comprises a system.

5. The apparatus of claim 1, wherein each charge storage device comprises a floating gate transistor.

6. The apparatus of claim 1, wherein each charge storage device comprises a charge trap transistor.

7. The apparatus of claim 1, wherein the pillar extends from a data line to a well in a substrate.

8. The apparatus of claim 1, wherein the pillar comprises polysilicon.

9. The apparatus of claim 1, wherein:

the string is one of a plurality of strings; and

the source select device is one of a plurality of source select devices, wherein each of the plurality of source select devices is between a corresponding one of the plurality of strings and the source gate device.

10. The apparatus of claim 1, wherein:

the string is one of a plurality of strings; and

the source select device is coupled between the plurality of strings and the source gate device.

11. An apparatus comprising:

a plurality of strings of charge storage devices, each string comprising a respective plurality of charge storage devices associated with a respective pillar comprising semiconductor material;

a drain select gate at least partially surrounding the respective pillars of the plurality of strings, wherein the drain select gate is between the plurality of strings of charge storage devices and respective data lines;

a source gate at least partially surrounding the respective pillars of the plurality of strings, the source gate coupled to a source and configured to control conduction between the pillar and the source; and

a source select gate at least partially surrounding the respective pillars of the plurality of strings, wherein the source select gate is between the plurality of strings of charge storage devices and the source gate and configured to control conduction between the pillar and the source.

12. The apparatus of claim 11, wherein:

the plurality of strings comprises two strings; and

wherein each of the drain select gate, the source gate and the source select gate at least partially surrounds two pillars associated with the two strings.

13. The apparatus of claim 11, wherein the plurality of strings comprise a sub-block of a block of strings, wherein the sub-block is separated from a neighboring sub-block of the block of strings by a diffusion region.

14. The apparatus of claim 11, wherein:

the drain select gate comprises a portion of a drain select device; and

the source select gate comprises a portion of a source select device.

15. The apparatus of claim 11, wherein the source gate comprises a portion of a source gate device.

16. An apparatus comprising:

a plurality of blocks, each block comprising a plurality of strings, each string comprising a plurality of charge storage devices associated with a respective pillar extending from a substrate, the pillars comprising semiconductor material; and

a conductive member coupled to the substrate between groups of a plurality of the blocks, wherein the conductive member is configured to bias a common source of the strings;

wherein a respective one of the pillars comprises;

a drain select device associated with the respective pillar and coupled between the respective string and a data line;

a source select device associated with the respective pillar and coupled to the respective string; and

a source gate device associated with the respective pillar and coupled between the source select device and the common source, wherein the source select device and the source gate device are configured to substantially control conduction between the pillar and the common source.

17. The apparatus of claim 16, wherein:

the substrate comprises a p-type substrate; and

the conductive member is coupled to an n+ type diffusion region in the p-type substrate.

18. The apparatus of claim 17, further comprising a plurality of n+ type diffusion regions in the p-type substrate, including the n+ type diffusion region.

19. The apparatus of claim 16, wherein the conductive member has a wall shape that projects from the substrate.

20. The apparatus of claim 16, wherein the conductive member comprises a semiconductor material.

21. The apparatus of claim 20, wherein the conductive member comprises polysilicon.

22. The apparatus of claim 16, wherein the conductive member comprises metal.

23. A method comprising:

biasing a first drain select gate to a first voltage above 0 volts, the first drain select gate at least partially surrounding respective pillars of a first plurality of strings of charge storage devices, wherein the first drain select gate is between the first plurality of strings and respective data lines;

biasing a second drain select gate to approximately 0 volts, the second drain select gate at least partially surrounding respective pillars of a second plurality of strings of charge storage devices, the second drain select gate being between the second plurality of strings and the data lines, each string comprising a respective plurality of charge storage devices associated with a respective pillar comprising semiconductor material extending from a common source;

biasing the common source to approximately 0 volts;

biasing a source gate to a second voltage above the first voltage, the source gate at least partially surrounding the respective pillars of the first plurality of strings and the second plurality of strings, wherein the source gate is between the charge storage devices and the common source;

biasing a first source select gate to the first voltage, the first source select gate at least partially surrounding the respective pillars of the first plurality of strings, wherein the first source select gate is between the first plurality of strings and the source gate;

biasing a second source select gate to approximately 0 volts, the second source select gate at least partially surrounding the respective pillars of the second plurality of strings, wherein the second source select gate is between the second plurality of strings and the source gate;

biasing a plurality of first access lines to a third voltage above the second voltage, the first access lines at least partially surrounding the respective pillars of the first plurality of strings, wherein the first access lines are between the first drain select gate and the first source select gate;

biasing a selected one of first access lines to between 0 volts and the first voltage to read a charge storage device in the first plurality of strings at least partially surrounded by the selected first access line; and

biasing a plurality of second access lines to the third voltage, the second access lines at least partially surrounding the respective pillars of the second plurality of strings, wherein the second access lines are between the second drain select gate and the second source select gate.

24. A method comprising:

biasing a first drain select gate to a first voltage above 0 volts, the first drain select gate at least partially surrounding respective pillars of a first plurality of strings of charge storage devices, wherein the first drain select gate is between the first plurality of strings and respective data lines;

biasing a second drain select gate to approximately 0 volts, the second drain select gate at least partially surrounding respective pillars of a second plurality of strings of charge storage devices, the second drain select gate being between the second plurality of strings and the data lines, each string comprising a respective plurality of charge storage devices associated with a respective pillar comprising semiconductor material extending from a common source;

biasing the common source to between 0 volts and the first voltage;

biasing a source gate to approximately 0 volts, the source gate at least partially surrounding the respective pillars of the first plurality of strings and the second plurality of strings, wherein the source gate is between the charge storage devices and the common source;

biasing a first source select gate to between 0 volts and the first voltage, the first source select gate at least partially surrounding the respective pillars of the first plurality of strings, wherein the first source select gate is between the first plurality of strings and the source gate;

biasing a second source select gate to between 0 volts and the first voltage, the second source select gate at least partially surrounding the respective pillars of the second plurality of strings, wherein the second source select gate is between the second plurality of strings and the source gate;

biasing a plurality of first access lines to a second voltage above the first voltage, the first access lines at least partially surrounding the respective pillars of the first plurality of strings, wherein the first access lines are between the first drain select gate and the first source select gate;

biasing a selected one of first access lines to a third voltage above the second voltage to program a charge storage device in the first plurality of strings at least partially surrounded by the selected first access line; and

biasing a plurality of second access lines to the second voltage, the second access lines at least partially surrounding the respective pillars of the second plurality of strings, wherein the second access lines are between the second drain select gate and the second source select gate.

25. A method comprising:

allowing a first drain select gate to float, the first drain select gate at least partially surrounding respective pillars of a first plurality of strings of charge storage devices, wherein the first drain select gate is between the first plurality of strings and respective data lines;

allowing a second drain select gate to float, the second drain select gate at least partially surrounding respective pillars of a second plurality of strings of charge storage devices, the second drain select gate being between the second plurality of strings and the data lines, each string comprising a respective plurality of charge storage devices associated with a respective pillar comprising semiconductor material extending from a common source in a substrate;

biasing the substrate to an erase voltage above 0 volts;

allowing the common source to float;

allowing a source gate to float, the source gate at least partially surrounding the respective pillars of the first plurality of strings and the second plurality of strings, wherein the source gate is between the charge storage devices and the common source;

allowing a first source select gate to float, the first source select gate at least partially surrounding the respective pillars of the first plurality of strings, wherein the first source select gate is between the first plurality of strings and the source gate;

allowing a second source select gate to float, the second source select gate at least partially surrounding the respective pillars of the second plurality of strings, wherein the second source select gate is between the second plurality of strings and the source gate;

biasing a plurality of first access lines to approximately 0 volts, the first access lines at least partially surrounding the respective pillars of the first plurality of strings to erase charge storage devices in the first plurality of strings, wherein the first access lines are between the first drain select gate and the first source select gate; and

biasing a plurality of second access lines to approximately 0 volts, the second access lines at least partially surrounding the respective pillars of the second plurality of strings to erase charge storage devices in the second plurality of strings, wherein the second access lines are between the second drain select gate and the second source select gate.