Synchronizing receivers in a signal acquisition system

• US 8,798,207 B2
• Filed: 06/20/2012
• Issued: 08/05/2014
• Est. Priority Date: 06/20/2012
• Status: Active Grant

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Wertz, Daniel S., Hinde, Andrew J., Ammerman, Johnathan R. W.
• Primary Examiner(s): NEFF, MICHAEL R
• Application Number:
  US13/528,081
• Publication Number:
  US 20130343490A1
• Time in Patent Office: 776 Days
• Field of Search: 375/340
• US Class Current: 375/340
• CPC Class Codes: H04B 17/21 for calibration; for correcting measurements
• CPC Class Codes: H04L 7/0029 interpolation of received data signal

Abstract

A system and method for synchronizing a plurality of receivers. A tone from a signal generator is swept over a frequency band. A power splitter splits the tone into a plurality of resultant tones that are supplied to the respective receivers. For each receiver, a relative frequency response (including amplitude and phase responses) is measured between the receiver and a master receiver. A linear approximation to the phase response is computed. A digital filter is custom designed for the receiver to compensate for non-uniformity of the amplitude response and for deviations of the phase from the linear approximation. After applying the digital filter, further adjustments are made to remove the time delay corresponding to the linear approximation, e.g., by appropriately configuring a fractional resampler, by adjusting a numerically-controlled oscillator, and/or, by adjusting sample clock phase.

Claims

1. A computer-implemented method for synchronizing a plurality of receiver channels, the method comprising:

calibrating the plurality of receiver channels, wherein said calibrating synchronizes the plurality of receiver channels, wherein one of the receiver channels is designated as a master channel, wherein the one or more remaining receiver channels are designated as slave channels, wherein each of the receiver channels includes a signal path that is configured to;

down-convert a respective input signal to obtain a respective IF (intermediate frequency) signal, digitize the respective IF signal based on a respective sample clock to obtain a respective IF sample sequence, digitally down-convert the respective IF sample sequence to obtain a respective baseband sample sequence;

wherein said calibrating the plurality of receiver channels includes, for each of the slave channels;

computing a relative frequency response between the slave channel and the master channel, wherein the relative frequency response is based on the respective baseband sample sequence of the slave channel and the respective baseband sample sequence of the master channel;

computing a digital filter for the slave channel based on the relative frequency response, wherein the digital filter is configured to compensate for non-uniformity in amplitude of the relative frequency response and for a deviation of phase of the relative frequency response from a linear approximation of the phase of the relative frequency response;

programming a digital circuit of the slave channel to implement the digital filter, wherein, after said programming, the digital circuit of the slave channel applies the digital filter to the respective IF sample sequence prior to said digital down-converting of the respective IF sample sequence.

2. The method of claim 1, wherein said calibrating also includes:

executing a first computer program that causes the sample clocks of the respective receiver channels to be more closely aligned in time than prior to said executing first computer program, wherein said computing a relative frequency response for each of the slave channels is performed after having executed the first computer program.

3. The method of claim 1, wherein said calibrating also includes, for each of the slave channels:

computing an updated relative phase response between the slave channel and the master channel after having performed said programming;

computing a slope of the updated relative phase response;

directing the slave channel to apply a time delay to its signal path, wherein the value of the time delay is based on the computed slope.

4. The method of claim 3, wherein said directing the slave channel to apply the time delay includes adjusting a phase of the sample clock of the slave channel based on the computed slope.

5. The method of claim 3, wherein said calibrating also includes, for each of the slave channels, modifying the digital filter of the slave channel to include the corresponding time delay, wherein said directing the slave channel to apply the time delay includes programming the digital circuit of the slave channel to implement the modified digital filter.

6. The method of claim 3, wherein said calibrating also includes, for each of the slave channels, generating coefficients for a fractional resampler, wherein said directing the slave channel to apply the time delay includes programming the digital circuit to implement the fractional resampler in addition to the digital filter.

7. The method of claim 3, wherein said calibrating also includes, for each of the slave channels:

computing a second updated relative phase response between the slave channel and the master channel after having performed said directing the slave channel to apply the time delay to its signal path;

computing a residual slope of the second updated relative phase response;

adjusting a phase of the sample clock of the slave channel based on the computed residual slope.

8. The method of claim 7, wherein each of the receiver channels includes a corresponding numerically controlled oscillator (NCO) configured to generate an orthogonal pair of digital sinusoids having programmable phase and programmable frequency, wherein said calibrating also includes, for each of the slave channels:

computing a third updated relative phase response between the slave channel and the master channel after said adjusting the phase of the sample clock of the slave channel;

computing an average phase value of the corresponding third updated relative phase response;

adjusting the phase of the corresponding numerically controlled oscillator in order to remove the corresponding average phase value.

9. The method of claim 1, wherein the designation of which receiver channel is to be the master channel is software controlled.

10. The method of claim 1, wherein each of the receiver channels is also configured to digitally generate a respective trigger clock from the respective sample clock signal, wherein the respective trigger clock is used to condition a reception of a trigger signal, wherein the trigger signal is used to determine a start of acquisition of the respective baseband sample sequence into a respective memory.

11. A non-transitory computer-readable memory medium for synchronizing a plurality of receiver channels, wherein the memory medium stores program instructions, wherein the program instructions, when executed by a computer system, cause the computer system to:

calibrate the plurality of receiver channels, wherein said calibrating synchronizes the plurality of receiver channels, wherein one of the receiver channels is designated as a master channel, wherein the one or more remaining receiver channels are designated as slave channels, wherein each of the receiver channels includes a signal path that is configured to;

down-convert a respective input signal to obtain a respective IF (intermediate frequency) signal, digitize the respective IF signal based on a respective sample clock to obtain a respective IF sample sequence, digitally down-convert the respective IF sample sequence to obtain a respective baseband sample sequence;

wherein said calibrating the plurality of receiver channels includes, for each of the slave channels;

computing a relative frequency response between the slave channel and the master channel, wherein the relative frequency response is based on the respective baseband sample sequence of the slave channel and the respective baseband sample sequence of the master channel;

computing a digital filter for the slave channel based on the relative frequency response, wherein the digital filter is configured to compensate for non-uniformity in amplitude of the relative frequency response and for a deviation of phase of the relative frequency response from a linear approximation of the phase of the relative frequency response;

programming a digital circuit of the slave channel to implement the digital filter, wherein, after said programming, the digital circuit of the slave channel applies the digital filter to the respective IF sample sequence prior to said digital down-converting of the respective IF sample sequence.

12. The memory medium of claim 11, wherein said calibrating also includes:

executing a first computer program that causes the sample clocks of the respective receiver channels to be more closely aligned in time than prior to said executing first computer program, wherein said computing a relative frequency response for each of the slave channels is performed after having executed the first computer program.

13. The memory medium of claim 11, wherein said calibrating also includes, for each of the slave channels:

computing an updated relative phase response between the slave channel and the master channel after having performed said programming;

computing a slope of the updated relative phase response;

directing the slave channel to apply a time delay to its signal path, wherein the value of the time delay is based on the computed slope.

14. The memory medium of claim 13, wherein said directing the slave channel to apply the time delay includes adjusting a phase of the sample clock of the slave channel based on the computed slope.

15. The memory medium of claim 13, wherein said calibrating also includes, for each of the slave channels, modifying the digital filter of the slave channel to include the corresponding time delay, wherein said directing the slave channel to apply the time delay includes programming the digital circuit of the slave channel to implement the modified digital filter.

16. The memory medium of claim 13, wherein said calibrating also includes, for each of the slave channels, generating coefficients for a fractional resampler, wherein said directing the slave channel to apply the time delay includes programming the digital circuit to implement the fractional resampler in addition to the digital filter.

17. The memory medium of claim 13, wherein said calibrating also includes, for each of the slave channels:

computing a second updated relative phase response between the slave channel and the master channel after having performed said directing the slave channel to apply the time delay to its signal path;

computing a residual slope of the second updated relative phase response;

adjusting a phase of the sample clock of the slave channel based on the computed residual slope.

18. The memory medium of claim 17, wherein each of the receiver channels includes a corresponding numerically controlled oscillator (NCO) configured to generate an orthogonal pair of digital sinusoids having programmable phase and programmable frequency, wherein said calibrating also includes, for each of the slave channels:

computing a third updated relative phase response between the slave channel and the master channel after said adjusting the phase of the sample clock of the slave channel;

computing an average phase value of the corresponding third updated relative phase response;

adjusting the phase of the corresponding numerically controlled oscillator in order to remove the corresponding average phase value.

19. The memory medium of claim 11, wherein the designation of which receiver channel is to be the master channel is software controlled.

20. The memory medium of claim 11, wherein each of the receiver channels is also configured to digitally generate a respective trigger clock from the respective sample clock signal, wherein the respective trigger clock is used to condition a reception of a trigger signal, wherein the trigger signal is used to determine a start of acquisition of the respective baseband sample sequence into a respective memory.

21. A computer system for synchronizing a plurality of receiver channels, the computer system comprising:

a processor; and

memory storing program instructions, wherein the program instructions, when executed by the processor, cause the processor to;

calibrate the plurality of receiver channels, wherein said calibrating synchronizes the plurality of receiver channels, wherein one of the receiver channels is designated as a master channel, wherein the one or more remaining receiver channels are designated as slave channels, wherein each of the receiver channels includes a signal path that is configured to;

down-convert a respective input signal to obtain a respective IF (intermediate frequency) signal, digitize the respective IF signal based on a respective sample clock to obtain a respective IF sample sequence, digitally down-convert the respective IF sample sequence to obtain a respective baseband sample sequence, wherein said calibrating the plurality of receiver channels includes, for each of the slave channels;

computing a relative frequency response between the slave channel and the master channel, wherein the relative frequency response is based on the respective baseband sample sequence of the slave channel and the respective baseband sample sequence of the master channel;

computing a digital filter for the slave channel based on the relative frequency response, wherein the digital filter is configured to compensate for non-uniformity in amplitude of the relative frequency response and for a deviation of phase of the relative frequency response from a linear approximation of the phase of the relative frequency response; and

programming a digital circuit of the slave channel to implement the digital filter, wherein, after said programming, the digital circuit of the slave channel applies the digital filter to the respective IF sample sequence prior to said digital down-converting of the respective IF sample sequence.

22. A computer-implemented method for synchronizing a second receiver with respect to a first receiver, the method comprising:

calibrating the second receiver, wherein said calibrating synchronizes the second receiver to the first receiver, wherein each receiver includes a signal path that is configured to;

receive a respective input signal, down-convert the respective input signal to obtain a respective IF signal, digitize the respective IF signal based on a respective sample clock to obtain a respective IF sample sequence, digitally down-convert the respective IF sample sequence to obtain a respective baseband sample sequence, wherein said calibrating the second receiver includes;

computing a relative frequency response of the second receiver with respect to the first receiver based on the respective baseband sample sequence of the second receiver and the respective baseband sample sequence of the first receiver;

computing a digital filter for the second receiver based on the relative frequency response, wherein the digital filter is configured to compensate for non-uniformity in amplitude of the relative frequency response and for a deviation of phase of the relative frequency response from a linear approximation of the phase of the relative frequency response;

programming a digital circuit of the second receiver to implement the digital filter, wherein, after said programming, the digital circuit applies the digital filter to the IF sample sequence of the second receiver prior to said digital down-converting of that IF sample sequence.

23. The method of claim 22, wherein said calibrating the second receiver also includes:

executing a first computer program that causes the sample clock of the second receiver to be more closely aligned in time to the sample clock of the first receiver, wherein said computing a relative frequency response is performed after having executed the first computer program.

24. The method of claim 22, wherein said calibrating the second receiver also includes:

computing an updated relative phase response of the second receiver relative to the first receiver after having performed said programming;

computing a slope of the updated relative phase response;

directing the second receiver to apply a time delay to its signal path, wherein the value of the time delay is based on the computed slope.

25. The method of claim 24, wherein said calibrating the second receiver also includes:

computing a second updated relative phase response of the second receiver relative to the first receiver after having performed said directing the second receiver to apply the time delay to its signal path;

computing a residual slope of the second updated relative phase response;

adjusting a phase of the sample clock of the second receiver based on the residual slope.

26. The method of claim 25, wherein the second receiver includes a numerically controlled oscillator configured to generate an orthogonal pair of digital sinusoids having programmable phase and programmable frequency, wherein said calibrating the second receiver also includes:

computing a third updated relative phase response of the second receiver relative to the first receiver after having performed said adjusting the phase of the sample clock of the second receiver;

computing an average phase value of the third updated relative phase response;

adjusting the phase of the numerically controlled oscillator of the second receiver in order to remove the average phase value.