Linear to physical address translation with support for page attributes

• US 8,799,620 B2
• Filed: 06/01/2007
• Issued: 08/05/2014
• Est. Priority Date: 06/01/2007
• Status: Active Grant

• Current Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Original Assignee: Intel Corporation
• Inventors: Falik, Ohad, Friedman, Ben-Zion, Doweck, Jack, Weissmann, Eliezer, Crossland, James B.
• Primary Examiner(s): Bradley, Matthew
• Assistant Examiner(s): Talukdar, Arvind
• Application Number:
  US11/757,103
• Publication Number:
  US 20080301398A1
• Time in Patent Office: 2,622 Days
• Field of Search: 711/207
• US Class Current: 711/206
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/507 using speculative control
• CPC Class Codes: G06F 2212/65 Details of virtual memory and virtual address translation
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 2212/68 Details of translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/684 TLB miss handling
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/342 Extension of operand address space

Abstract

Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Claims

1. A machine-implemented method comprising:

receiving an instruction to translate a virtual memory pointer to a physical memory address for a memory location without accessing data stored at the physical memory address in response to the instruction;

translating the virtual memory pointer to the physical memory address based on page table information; and

returning in one or more registers, as a result of the instruction to translate the virtual memory pointer to the physical memory address for the memory location without accessing data stored at the physical memory address in response to the instruction, the physical memory address and one or more page attributes without returning data stored at the physical memory address in response to the instruction, the one or more page attributes including a set of access bits,

wherein returning in said one or more registers, the physical memory address and the one or more page attributes in response to the instruction comprises;

obtaining the physical memory address and the one or more page attributes from a translation look-aside buffer entry to return in said one or more registers in response to the instruction.

2. The method of claim 1, wherein translating the virtual memory pointer to the physical memory address based on page table information comprises:

reading a translation look-aside buffer (TLB) entry to obtain the physical memory address and the one or more page attributes.

3. The method of claim 1, wherein translating the virtual memory pointer to the physical memory address based on page table information comprises:

if a TLB does not contain the physical memory address, then reading at least one page table entry to obtain the physical memory address and the one or more page attributes.

4. The method of claim 1, wherein the one or more attributes include at least one of:

a present bit,

a read/write bit,

a user/supervisor bit,

an access bit,

a dirty bit,

a global flag,

an execute disable bit,

a page size indicator, and

a translation page fault.

5. The method of claim 1 wherein returning the physical memory address and the one or more page attributes comprises:

storing the physical memory address and the one or more page attributes in a dedicated register; and

accessing the dedicated register using, at least in part, microcode.

6. The method of claim 1, wherein returning the physical memory address and the one or more page attributes comprises:

returning the physical memory address and the one or more page attributes via a read return bus.

7. The method of claim 1, wherein receiving the instruction to translate the virtual memory pointer to a physical memory address for a memory location includes receiving the instruction from a virtual machine manager;

and further wherein returning the physical memory address and the one or more page attributes includes returning a host physical memory address.

8. The method of claim 1, wherein receiving the instruction to translate the virtual memory pointer to a physical memory address for a memory location includes receiving the instruction from a guest operating system;

and further wherein returning the physical memory address and the one or more page attributes includes returning a guest physical memory address.

9. The method of claim 1, wherein receiving the instruction to translate the virtual memory pointer to a physical memory address for a memory location comprises:

receiving an instruction to translate the virtual memory pointer to a physical memory address, the instruction including an operand to define a context for the instruction.

10. The method of claim 1, wherein translating the virtual memory pointer to the physical memory address based on page table information comprises:

determining whether a page corresponding to the virtual memory pointer is in memory without using page table information.

11. A system comprising:

a memory device; and

a processor and logic executable thereon to

receive an instruction to translate a virtual memory pointer to a physical memory address for a memory location without accessing data stored at the physical memory address in response to the instruction;

translate the virtual memory pointer to the physical memory address based on page table information; and

return in one or more registers, as a result of the instruction to translate the virtual memory pointer to the physical memory address for the memory location without accessing data stored at the physical memory address in response to the instruction, the physical memory address and one or more page attributes without returning data stored at the physical memory address in response to the instruction, the one or more page attributes including a set of access bits,

wherein returning in said one or more registers, the physical memory address and the one or more page attributes in response to the instruction comprises;

obtaining the physical memory address and the one or more page attributes from a translation look-aside buffer entry to return in said one or more registers in response to the instruction.

12. The system of claim 11, wherein the logic to translate the virtual memory pointer to the physical memory address based on page table information comprises:

logic to read a translation look-aside buffer (TLB) entry to obtain the physical memory address and the one or more page attributes.

13. The system of claim 11, wherein the logic to translate the virtual memory pointer to the physical memory address based on page table information comprises:

logic to read a page table entry to obtain the physical memory address and the one or more page attributes, if a TLB does not contain the physical memory address.

14. The system of claim 11, wherein the one or more attributes include at least one of:

a present bit,

a read/write bit,

a user/supervisor bit,

an access bit,

a dirty bit,

a global flag,

an execute disable bit,

a page size indicator, and

a translation page fault.

15. The system of claim 11, wherein the logic to receive the instruction to translate the virtual memory pointer to a physical memory address for a memory location includes

logic to receive the instruction from a virtual machine manager;

and

further wherein the logic to return the physical memory address and the one or more page attributes includes logic to return a host physical memory address.

16. An article of manufacture including an apparatus to perform a machine-specific machine-implemented operation, the apparatus having address translation logic operatively coupled with a machine-readable medium comprising instructions which, if executed by the apparatus, cause the apparatus to:

receive an instruction to translate a virtual memory pointer to a physical memory address for a memory location without accessing data stored at the physical memory address in response to the instruction;

translate the virtual memory pointer to the physical memory address based on page table information; and

return in one or more registers, as a result of the received instruction to translate the virtual memory pointer to the physical memory address for the memory location without accessing data stored at the physical memory address in response to the instruction, the physical memory address and one or more page attributes without returning data stored at the physical memory address in response to the instruction, the one or more page attributes including a set of access bits,

wherein returning in said one or more registers, the physical memory address and the one or more page attributes in response to the instruction comprises;

obtaining the physical memory address and the one or more page attributes from a translation look-aside buffer entry to return in said one or more registers in response to the instruction.

17. The article of manufacture of claim 16, wherein the instructions that, when executed by the apparatus, cause the apparatus to translate the virtual memory pointer to the physical memory address based on page table information cause the apparatus to:

read a translation look-aside buffer (TLB) entry to obtain the physical memory address and the one or more page attributes.

18. The article of manufacture of claim 16, wherein the instructions that, when executed by the apparatus, cause the apparatus to translate the virtual memory pointer to the physical memory address based on page table information cause the apparatus to:

read a page table entry to obtain the physical memory address and the one or more page attributes, if a TLB does not contain the physical memory address.

19. The article of manufacture of claim 16, wherein the one or more attributes include at least one of:

a present bit,

a read/write bit,

a user/supervisor bit,

an access bit,

a dirty bit,

a global flag,

an execute disable bit,

a page size indicator, and

a translation page fault.

20. The article of manufacture of claim 16, wherein the instructions that, when executed by the apparatus, cause the apparatus to

receive the instruction to translate the virtual memory pointer to a physical memory address for a memory location cause the apparatus to receive the instruction from a virtual machine manager;

and

further wherein the instructions that, when executed by the apparatus, cause the apparatus to return the physical memory address and the one or more page attributes cause the apparatus to return a host physical memory address.

21. A machine-implemented method comprising:

receiving an instruction to translate a virtual memory pointer to a physical memory address for a memory location without accessing data stored at the physical memory address in response to the instruction;

translating the virtual memory pointer to the physical memory address based on page table information; and

returning, as a result of the instruction to translate the virtual memory pointer to the physical memory address for the memory location without accessing data stored at the physical memory address in response to the instruction, the physical memory address and one or more page attributes without returning data stored at the physical memory address in response to the instruction, the one or more page attributes including a global flag;

wherein returning the physical memory address and the one or more page attributes in response to the instruction comprises;

reading a translation look-aside buffer (TLB) entry to obtain the physical memory address and the one or more page attributes; and

returning in one or more registers, the physical memory address and the one or more page attributes as a result of the instruction.

26. The method of claim 21, wherein receiving the instruction to translate the virtual memory pointer to a physical memory address for a memory location includes receiving the instruction from a guest operating system;

and further wherein returning the physical memory address and the one or more page attributes in response to the instruction includes returning a guest physical memory address.

22. A machine-implemented method comprising:

receiving an instruction to translate a virtual memory pointer to a physical memory address for a memory location without accessing data stored at the physical memory address in response to the instruction;

translating the virtual memory pointer to the physical memory address based on page table information; and

returning, as a result of the instruction to translate the virtual memory pointer to the physical memory address for the memory location without accessing data stored at the physical memory address in response to the instruction, the physical memory address and one or more page attributes without returning data stored at the physical memory address in response to the instruction, the one or more page attributes including a translation page fault;

wherein returning the physical memory address and the one or more page attributes in response to the instruction comprises;

reading a translation look-aside buffer (TLB) entry to obtain the physical memory address and the one or more page attributes; and

returning in one or more registers, the physical memory address and the one or more page attributes as a result of the instruction.

25. The method of claim 22, wherein returning the physical memory address and the one or more page attributes in response to the instruction comprises:

storing the physical memory address and the one or more page attributes in a dedicated register; and

accessing the dedicated register using, at least in part, microcode.

23. A machine-implemented method comprising:

receiving an instruction to translate a virtual memory pointer to a physical memory address for a memory location without accessing data stored at the physical memory address in response to the instruction;

translating the virtual memory pointer to the physical memory address based on page table information; and

returning in one or more registers, as a result of the instruction to translate the virtual memory pointer to the physical memory address for the memory location without accessing data stored at the physical memory address in response to the instruction, the physical memory address and one or more page attributes without returning data stored at the physical memory address in response to the instruction, the one or more page attributes including a set of access bits and a page size indication;

wherein returning the physical memory address and the one or more page attributes in response to the instruction comprises;

reading a translation look-aside buffer (TLB) entry to obtain the physical memory address and the one or more page attributes; and

returning in said one or more registers, the physical memory address and the one or more page attributes as a result of the instruction.

24. The method of claim 23, wherein translating the virtual memory pointer to the physical memory address based on page table information comprises:

if a TLB does not contain the physical memory address, then reading at least one page table entry to obtain the physical memory address and the one or more page attributes.