Information handling system with processing system, low-power processing system and shared resources
First Claim
1. An information handling system comprising:
- a chipset including;
a low power processor configured to be disabled during operation of a power processing system in the information handling system;
a processor configured to be disabled during operation of a low power processing system in the information handling system; and
a switching module, the switching module configured to enable the processor to access one or more shared resources during operation of the processing system, and configured to enable the low power processor to access one or more non-shared resources during operation of the low power processing system.
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Accused Products
Abstract
An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.
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Citations
21 Claims
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1. An information handling system comprising:
a chipset including; a low power processor configured to be disabled during operation of a power processing system in the information handling system; a processor configured to be disabled during operation of a low power processing system in the information handling system; and a switching module, the switching module configured to enable the processor to access one or more shared resources during operation of the processing system, and configured to enable the low power processor to access one or more non-shared resources during operation of the low power processing system. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A chipset comprising:
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a low power processor configured to be disabled during operation of a processing system in an information handling system; a processor configured to be disabled during operation of a low power processing system in the information handling system; a switching module, the switching module configured to enable the processor to access one or more shared resources during operation of the processing system, and configured to enable the low power processor to access one or more non-shared resources during operation of the low power processing system; and a video multiplexing layer powered by a power system, the video multiplexing layer configured to receive a processing system video input and a low power processing system video input, and to up-scale a video output by combining the processing system video input with the low power processing system video input prior to outputting the video output. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. An information handling system comprising:
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a chipset including; a low power processor configured to be disabled during operation of a processing system in an information handling system; a processor configured to be disabled during operation of a low power processing system in the information handling system; and a switching module, the switching module configured to enable the processor to access one or more shared resources during operation of the processing system, and configured to enable the low power processor to access one or more non-shared resources during operation of the low power processing system; and a video raster coupled to the chipset and operable to be accessed as a shared video output resource by the processor and by the low power processor. - View Dependent Claims (18, 19, 20, 21)
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Specification