Method for manufacturing high density non-volatile magnetic memory

• US 8,802,451 B2
• Filed: 09/11/2012
• Issued: 08/12/2014
• Est. Priority Date: 02/29/2008
• Status: Active Grant

• Current Assignee: Avalanche Technology Incorporated
• Original Assignee: Avalanche Technology Incorporated
• Inventors: Malmhall, Roger Klas, Satoh, Kimihiro, Zhang, Jing, Keshtbod, Parviz, Ranjan, Rajiv Yadav
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US13/610,587
• Publication Number:
  US 20130244344A1
• Time in Patent Office: 700 Days
• Field of Search: 438/3, 257/295, 257/421, 257/E27.005, 257/E43.006
• US Class Current: 438/3
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 25/00 Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: H10N 50/01 Manufacture or treatment

Abstract

Methods of fabricating MTJ arrays using two orthogonal line patterning steps are described. Embodiments are described that use a self-aligned double patterning method for one or both orthogonal line patterning steps to achieve dense arrays of MTJs with feature dimensions one half of the minimum photo lithography feature size (F). In one set of embodiments, the materials and thicknesses of the stack of layers that provide the masking function are selected so that after the initial set of mask pads have been patterned, a sequence of etching steps progressively transfers the mask pad shape through the multiple mask layer and down through all of the MTJ cell layers to the form the complete MTJ pillars. In another set of embodiments, the MTJ/BE stack is patterned into parallel lines before the top electrode layer is deposited.

Claims

1. A method for fabricating thin film magnetic memory cells on a wafer comprising:

depositing a stack of layers for a magnetic memory device on a substrate;

depositing a lower dielectric layer over the stack of layers for a magnetic memory device;

depositing a metal layer over the lower dielectric layer;

depositing an upper dielectric material layer over the metal layer;

patterning a first line mask of parallel lines of material;

forming parallel lines in the upper dielectric material by etching through the upper dielectric material layer using the first line mask;

patterning a second line mask over the parallel lines of upper dielectric material, the second line mask including parallel lines arranged orthogonally to the parallel lines of upper dielectric material and overlapping the parallel lines of upper dielectric material;

forming pads of upper dielectric material by etching through the parallel lines of upper dielectric layer using the second line mask; and

forming pillars of layers for the magnetic memory device on the substrate by executing a series of etching processes that successively transfer a shape of the pads of upper dielectric material into layers below the pads of upper dielectric material.

2. The method of claim 1 wherein patterning the first line mask of parallel lines of material further comprises:

patterning a set of parallel lines of sacrificial material using photo lithography;

depositing a layer of spacer material over the parallel lines of sacrificial material;

partially etching the layer of spacer material to leave parallel lines of spacer material disposed on first and second opposite sides of the parallel lines of sacrificial material; and

removing the parallel lines of sacrificial material to leave parallel lines of spacer material as the first line mask.

3. The method of claim 2 wherein patterning the second line mask of parallel lines of material further comprises:

patterning a set of parallel lines of sacrificial material using photo lithography;

depositing a layer of spacer material over the parallel lines of sacrificial material;

partially etching the layer of spacer material to leave parallel lines of spacer material disposed on first and second opposite sides of the parallel lines of sacrificial material; and

removing the parallel lines of sacrificial material to leave parallel lines of spacer material as the second line mask.

4. The method of claim 1 wherein patterning the second line mask of parallel lines of material further comprises:

patterning a set of parallel lines of sacrificial material using photo lithography;

depositing a layer of spacer material over the parallel lines of sacrificial material;

partially etching the layer of spacer material to leave parallel lines of spacer material disposed on first and second opposite sides of the parallel lines of sacrificial material; and

removing the parallel lines of sacrificial material to leave parallel lines of spacer material as the second line mask.

5. The method of claim 1 wherein forming pillars further comprises:

using a first etching process to etch through the metal layer using the pads of upper dielectric material as a mask to form bilayer pads having an upper pad layer of upper dielectric material and a lower pad layer of metal; and

using a second etching process to etch through the lower dielectric layer using the lower pad layer of metal as a mask.

6. The method of claim 1 wherein patterning a second line mask further comprises depositing a planarizing BARC layer over the parallel lines of upper dielectric material.

7. The method of claim 1 wherein the lower dielectric layer or the upper dielectric is an oxide.

8. The method of claim 1 wherein the lower dielectric layer or the upper dielectric is a nitride.

9. The method of claim 1 wherein the metal layer is copper.