Method for handling a semiconductor wafer assembly

• US 8,802,465 B2
• Filed: 09/21/2012
• Issued: 08/12/2014
• Est. Priority Date: 01/11/2005
• Status: Active Grant

• Current Assignee: Semileds Optoelectronics Company Limited (SemiLEDs Inc)
• Original Assignee: Semileds Optoelectronics Company Limited (SemiLEDs Inc)
• Inventors: Doan, Trung Tri, Chu, Chen-Fu
• Primary Examiner(s): Roman, Angel
• Application Number:
  US13/624,656
• Publication Number:
  US 20140087499A1
• Time in Patent Office: 690 Days
• Field of Search: 438 25- 28
• US Class Current: 438/28
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01S 5/0217 Removal of the substrate
• CPC Class Codes: H01S 5/02355 Fixing laser chips on mounts
• CPC Class Codes: H01S 5/04252 characterised by the material
• CPC Class Codes: H01S 5/04253 having specific optical properties, e.g. transparent electrodes
• CPC Class Codes: H01S 5/04257 having positive and negative electrodes on the same side of the substrate
• CPC Class Codes: H01S 5/18375 based on metal reflectors
• CPC Class Codes: H01S 5/34333 with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser

Abstract

Systems and methods for fabricating a light emitting diode include forming a multilayer epitaxial structure above a carrier substrate; depositing at least one metal layer above the multilayer epitaxial structure; removing the carrier substrate.

Claims

1. A method comprising:

providing a wafer assembly comprising a plurality of semiconductor dies on a carrier substrate, each die comprising a multi-layer epitaxial structure;

depositing a plurality of metal layers on the semiconductor dies configured as a metal substrate, the metal layers comprising;

a first stress-reducing layer on the epitaxial structure comprising a first material having a first hardness and a first thickness, with the first material and the first thickness selected to minimize cracking of the epitaxial structure;

a harder layer on the first stress-reducing layer comprising a second material having a second hardness greater than the first hardness and a second thickness, with the second material and the second thickness selected to allow handling of the wafer assembly without cracking of the epitaxial structure; and

a second stress-reducing layer on the harder layer comprising a third material having a third thickness, with the third material and the third thickness selected to compensate for stress from depositing of the harder layer;

removing the carrier substrate from the wafer assembly; and

manipulating the wafer assembly via the metal substrate for further processing.

2. The method of claim 1 wherein the first material comprises a material selected from the group consisting of Cu, Ag and Au, the second material comprises a material selected from the group consisting of Mo, W, Ni and Ni-Co, and the third material comprises Cu.

3. The method of claim 1 further comprising plasma treating a surface of the epitaxial structure prior to the depositing step.

4. The method of claim 1 further comprising depositing an oxidation protection layer on the second stress-reducing layer.

5. The method of claim 4 wherein the oxidation protection layer comprises a metal selected from the group consisting of Cr/Au, Ni, and Ni/Au.

6. A method comprising:

providing a wafer assembly comprising a plurality of semiconductor dies on a carrier substrate, each die comprising a multi-layer epitaxial structure having a thermal expansion coefficient;

depositing a plurality of metal layers on the semiconductor dies configured as a metal substrate, the metal layers comprising;

an initial layer on the epitaxial structure comprising a first metal having a first thickness and a first thermal expansion coefficient substantially matching the thermal expansion coefficient of the epitaxial structure and a first thermal conductivity, with the first metal and the first thickness selected to allow handling of the wafer assembly without cracking of the epitaxial structure;

a thermally conductive layer deposited on the initial layer comprising a second metal having a second thickness and a second thermal conductivity greater than the first thermal conductivity;

removing the carrier substrate from the wafer assembly; and

manipulating the wafer assembly via the metal substrate for further processing.

7. The method of claim 6 wherein the first metal comprises a material selected from the group consisting of W and Mo and the second metal comprises a material selected from the group consisting of Cu and Ag.

8. The method of claim 6 wherein the first metal comprises W and the second metal comprises Ag.

9. The method of claim 6 wherein the first metal comprises Mo and the second metal comprises Ag.

10. The method of claim 6 wherein the first metal comprises W or Mo and the second metal comprises Cu.