Method of manufacturing semiconductor device having metal gates

• US 8,802,524 B2
• Filed: 03/22/2011
• Issued: 08/12/2014
• Est. Priority Date: 03/22/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Liao, Po-Jui, Tsai, Tsung-Lung, Lin, Chien-Ting, Hsu, Shao-Hua, Chen, Yi-Wei, Huang, Hsin-Fu, Lee, Tzung-Ying, Tsai, Min-Chuan, Yang, Chan-Lon, Wu, Chun-Yuan, Tsai, Teng-Chun, Hwang, Guang-Yaw, Hsu, Chia-Lin, Yang, Jie-Ning, Chen, Cheng-Guo, Tseng, Jung-Tsung, Lee, Zhi-Cheng, Shih, Hung-Ling, Huang, Po-Cheng, Chen, Yi-Wen, Hsu, Che-Hua
• Primary Examiner(s): Smoot, Stephen W
• Assistant Examiner(s): Chin, Edward
• Application Number:
  US13/053,223
• Publication Number:
  US 20120244669A1
• Time in Patent Office: 1,239 Days
• Field of Search: 438/585, 438/275, 438/287, 438/591, 438/785, 438/216, 438/197, 438/104, 257/E21.309, 257/E21.634, 257/E21.444, 257/E21.62, 257/E21.623, 257/E21.633
• US Class Current: 438/212
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.

Claims

1. A method of manufacturing a semiconductor device having metal gates, comprising:

providing a substrate, wherein a first conductive type transistor and a second conductive type transistor are disposed on the substrate, and the first conductive type transistor comprises a first sacrifice gate and the second conductive type transistor comprises a second sacrifice gate;

removing the first sacrifice gate of the first conductive type transistor to form a first trench;

forming a first metal layer lining a sidewall and a bottom of the first trench without filling up the first trench;

removing the second sacrifice gate of the second conductive type transistor to form a second trench;

forming a second metal layer in the first trench and the second trench; and

forming a third metal layer on the second metal layer wherein the third metal layer completely fills the first trench and the second trench.

2. The method of manufacturing a semiconductor device having metal gates according to claim 1, after forming the third metal layer, further comprising:

performing a planarization process to simultaneously remove the first metal layer, the second metal layer and the third metal layer outside the first trench and the second trench.

3. The method of manufacturing a semiconductor device having metal gates according to claim 1, wherein the first type conductive transistor comprises a P type transistor and the second type conductive transistor comprises an N type transistor.

4. The method of manufacturing a semiconductor device having metal gates according to claim 3, wherein the first metal layer comprises Ni, Pd, Pt, Be, Ir, Te, Re, Ru, Rh, W, Mo, WN, RuN, MoN, TiN, TaN, WC, TaC, TiC, TiAlN or TaAlN.

5. The method of manufacturing a semiconductor device having metal gates according to claim 3, wherein the second metal layer comprises TiAl, ZrAl, WAl, TaAl or HfAl.

6. The method of manufacturing a semiconductor device having metal gates according to claim 3, before forming the third metal layer, further comprising forming a barrier layer on the second metal layer, wherein the barrier layer is filled into the first trench and the second trench.

7. The method of manufacturing a semiconductor device having metal gates according to claim 6, wherein the barrier layer comprises TiN.

8. The method of manufacturing a semiconductor device having metal gates according to claim 3, before forming the third metal layer, further comprising performing a passivating process on the second metal layer.

9. The method of manufacturing a semiconductor device having metal gates according to claim 8, wherein the passivating process comprises an oxidation process, a nitridation process or a process utilizing ammonia.

10. The method of manufacturing a semiconductor device having metal gates according to claim 1, wherein the first type conductive transistor comprises an N type transistor and the second type conductive transistor comprises a P type transistor.

11. The method of manufacturing a semiconductor device having metal gates according to claim 10, wherein the first metal layer comprises TiAl, ZrAl, WAl, TaAl or HfAl.

12. The method of manufacturing a semiconductor device having metal gates according to claim 10, wherein the second metal layer comprises Ni, Pd, Pt, Be, Ir, Te, Re, Ru, Rh, W, Mo, WN, RuN, MoN, TiN, TaN, WC, TaC, TiC, TiAlN or TaAlN.

13. The method of manufacturing a semiconductor device having metal gates according to claim 10, before forming the third metal layer, further comprising performing a passivating process on the second metal layer.

14. The method of manufacturing a semiconductor device having metal gates according to claim 13, wherein the passivating process comprises an oxidation process, a nitridation process or a process utilizing ammonia.

15. The method of manufacturing a semiconductor device having metal gates according to claim 1, wherein the third metal layer comprises Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti/W or Ti/TiN.

16. The method of manufacturing a semiconductor device having metal gates according to claim 1, wherein the step of removing the first sacrifice gate of the first conductive type transistor comprises:

forming a mask layer;

forming a first patterned photoresist layer to cover the second conductive type transistor;

performing a trimmed process toward the first patterned photoresist layer to form a second patterned photoresist layer, wherein the area of the second patterned photoresist layer is less than that of the first patterned photoresist layer;

removing the portions of the mask layer and the first sacrifice gate not covered by the second patterned photoresist layer;

removing the second patterned photoresist layer; and

performing a wet etching process to completely remove the first sacrifice gate.

17. The method of manufacturing a semiconductor device having metal gates according to claim 16, wherein the trimmed process uses a plasma gas comprising O₂, O₃, CF₄ or HBr.

18. The method of manufacturing a semiconductor device having metal gates according to claim 16, further comprising forming an auxiliary layer on the mask layer, wherein the auxiliary layer comprises SiO₂.

19. The method of manufacturing a semiconductor device having metal gates according to claim 1, after removing the first sacrifice gate, further comprising performing an annealing process.

20. The method of manufacturing a semiconductor device having metal gates according to claim 1, after removing the second sacrifice gate, further comprising performing an annealing process.