Semiconductor device
First Claim
1. A semiconductor device comprising:
- a first line;
a second line; and
a memory element, the memory element comprising;
a capacitor; and
a transistor, the transistor comprising;
a crystalline oxide semiconductor layer comprising oxygen, indium, zinc and a metal other than indium and zinc, the crystalline oxide semiconductor layer including a channel formation region; and
a gate electrode with a gate insulating film interposed between the channel formation region and the gate electrode,wherein one of a source and a drain of the transistor is electrically connected to the first line,wherein the other of the source and the drain of the transistor is electrically connected to one of terminals of the capacitor,wherein the other of the terminals of the capacitor is electrically connected to the second line,wherein a carrier concentration in the crystalline oxide semiconductor layer is less than or equal to 5×
1014 cm−
3, andwherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than 1×
10−
13 A.
1 Assignment
0 Petitions
Accused Products
Abstract
An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.
170 Citations
31 Claims
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1. A semiconductor device comprising:
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a first line; a second line; and a memory element, the memory element comprising; a capacitor; and a transistor, the transistor comprising; a crystalline oxide semiconductor layer comprising oxygen, indium, zinc and a metal other than indium and zinc, the crystalline oxide semiconductor layer including a channel formation region; and a gate electrode with a gate insulating film interposed between the channel formation region and the gate electrode, wherein one of a source and a drain of the transistor is electrically connected to the first line, wherein the other of the source and the drain of the transistor is electrically connected to one of terminals of the capacitor, wherein the other of the terminals of the capacitor is electrically connected to the second line, wherein a carrier concentration in the crystalline oxide semiconductor layer is less than or equal to 5×
1014 cm−
3, andwherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than 1×
10−
13 A. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor device comprising:
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a first line; a second line; and a memory element, the memory element comprising; a capacitor; and a transistor, the transistor comprising; a crystalline oxide semiconductor layer comprising oxygen, indium, zinc and a metal other than indium and zinc, the crystalline oxide semiconductor layer including a channel formation region; a gate electrode; and a first insulating layer over the gate electrode, wherein the channel formation region is provided over the gate electrode with the first insulating layer interposed therebetween, wherein one of a source and a drain of the transistor is electrically connected to the first line, wherein the other of the source and the drain of the transistor is electrically connected to one of terminals of the capacitor, wherein the other of the terminals of the capacitor is electrically connected to the second line, wherein a carrier concentration in the crystalline oxide semiconductor layer is less than or equal to 5×
1014 cm−
3, andwherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than 1×
10−
13 A. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A semiconductor device comprising:
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a memory element, the memory element comprising; a transistor, the transistor comprising; a crystalline oxide semiconductor layer comprising oxygen, indium, zinc and a metal other than indium and zinc, the crystalline oxide semiconductor layer including a channel formation region, wherein a carrier concentration in the crystalline oxide semiconductor layer is less than or equal to 5×
1014 cm−
3, andwherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than 1×
10−
13 A. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A processor comprising:
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a timing control circuit; an instruction decoder operationally connected to the timing control circuit; a register array; an address logic and buffer circuit operationally connected to the register array; a data bus interface operationally connected to the register array; an arithmetic logic unit operationally connected to the register array; and an instruction register operationally connected to the instruction decoder and the register array, wherein at least one of the register array and the instruction register comprises a memory element, wherein the memory element comprising a transistor comprising a crystalline oxide semiconductor layer comprising oxygen, indium, zinc and a metal other than indium and zinc, the crystalline oxide semiconductor layer including a channel formation region, and wherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than 1×
10−
13 A. - View Dependent Claims (19, 20, 21, 22, 23, 24)
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25. A processor comprising:
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a register array; an arithmetic logic unit operationally connected to the register array; and an instruction register operationally connected to the arithmetic logic unit, wherein at least one of the register array and the instruction register comprises a memory element, wherein the memory element comprising a transistor comprising a crystalline oxide semiconductor layer comprising oxygen, indium, zinc and a metal other than indium and zinc, the crystalline oxide semiconductor layer including a channel formation region, and wherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than 1×
10−
13 A. - View Dependent Claims (26, 27, 28, 29, 30, 31)
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Specification