Thin film transistor including buffer layers with high resistivity

• US 8,803,143 B2
• Filed: 10/12/2011
• Issued: 08/12/2014
• Est. Priority Date: 10/20/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): REIDA, MOLLY KAY
• Application Number:
  US13/271,518
• Publication Number:
  US 20120097941A1
• Time in Patent Office: 1,035 Days
• Field of Search: 257/43, 257/59, 257/72, 257/E21.461, 257/618, 257/619, 257/634, 257/E29.117, 257/151, 257/273, 257/E51.005, 438/29, 438/30, 438/149, 438/158, 438/199, 438/164, 438/201, 438/211, 438/238, 438/257, 438/597, 438/723, 438/724, 438/743, 438/744, 438/756, 438/757, 349/42, 349/45, 349/46, 349/122, 349/139, 349/142, 349/147
• US Class Current: 257/43
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A transistor in a display device is expected to have higher withstand voltage, and it is an object to improve the reliability of a transistor which is driven by high voltage or large current. A semiconductor device includes a transistor in which buffer layers are provided between a semiconductor layer forming a channel formation region and source and drain electrode layers. The buffer layers are provided between the semiconductor layer forming a channel formation region and the source and drain electrode layers in order to particularly relieve an electric field in the vicinity of a drain edge and improve the withstand voltage of the transistor.

Claims

1. A semiconductor device comprising:

a transistor comprising;

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

a semiconductor layer comprising a channel formation region over the gate insulating layer;

a buffer layer comprising an oxide of indium, a silicon oxide, and an oxide of tin over the semiconductor layer; and

a source electrode layer and a drain electrode layer over the buffer layer,

wherein the semiconductor layer is an oxide semiconductor layer,

wherein the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer through the buffer layer, and

wherein a percentage of the silicon oxide contained in the buffer layer is higher than or equal to 1 wt % and lower than or equal to 20 wt %.

2. The semiconductor device according to claim 1, wherein a side surface of the buffer layer has a tapered shape.

3. The semiconductor device according to claim 1, wherein an edge portion of the buffer layer exists between the channel formation region in the semiconductor layer and a lower edge portion of the source electrode layer and between the channel formation region in the semiconductor layer and a lower edge portion of the drain electrode layer.

4. The semiconductor device according to claim 1, wherein the semiconductor layer comprises indium, gallium, and zinc.

5. A semiconductor device comprising:

a transistor comprising;

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

a semiconductor layer comprising a channel formation region over the gate insulating layer;

a buffer layer comprising an oxide of indium, a silicon oxide, and an oxide of tin over the semiconductor layer; and

a source electrode layer and a drain electrode layer over the buffer layer,

wherein the semiconductor layer is an oxide semiconductor layer,

wherein the buffer layer is a metal oxide layer whose resistivity is higher than 1 Ω

cm,

wherein the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer through the buffer layer, and

wherein a percentage of the silicon oxide contained in the buffer layer is higher than or equal to 1 wt % and lower than or equal to 20 wt %.

6. The semiconductor device according to claim 5, wherein a side surface of the buffer layer has a tapered shape.

7. The semiconductor device according to claim 5, wherein an edge portion of the buffer layer exists between the channel formation region in the semiconductor layer and a lower edge portion of the source electrode layer and between the channel formation region in the semiconductor layer and a lower edge portion of the drain electrode layer.

8. The semiconductor device according to claim 5, wherein the semiconductor layer comprises indium, gallium, and zinc.

9. A semiconductor device comprising:

a transistor comprising;

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

a semiconductor layer comprising a channel formation region over the gate insulating layer;

first and second buffer layers over the semiconductor layer; and

a source electrode layer and a drain electrode layer over the first and second buffer layers,

wherein the semiconductor layer is an oxide semiconductor layer,

wherein the semiconductor layer is electrically connected to one of the source electrode layer and the drain electrode layer through one of the first and second buffer layers,

wherein one of the first and second buffer layers is a metal oxide layer whose resistivity is higher than 1 Ω

cm,

wherein the first and second buffer layers are metal oxide layers each comprising an oxide of indium, a silicon oxide, and an oxide of tin, and

wherein a percentage of the silicon oxide contained in one of the first and second buffer layers is higher than or equal to 1 wt % and lower than or equal to 20 wt %.

10. The semiconductor device according to claim 9, wherein the resistivity of the first buffer layer and the resistivity of the second buffer layer are different.

11. The semiconductor device according to claim 9, wherein a side surface of each of the first and second buffer layers has a tapered shape.

12. The semiconductor device according to claim 9, wherein edge portions of the first and second buffer layers exist between the channel formation region in the semiconductor layer and a lower edge portion of the source electrode layer and between the channel formation region in the semiconductor layer and a lower edge portion of the drain electrode layer.

13. The semiconductor device according to claim 9, wherein the semiconductor layer comprises indium, gallium, and zinc.