3D semiconductor device and structure

• US 8,803,206 B1
• Filed: 04/03/2013
• Issued: 08/12/2014
• Est. Priority Date: 12/29/2012
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Cronquist, Brian, Sekar, Deepak
• Primary Examiner(s): Parker, Kenneth
• Assistant Examiner(s): CULBERT, CHRISTOPHER A
• Application Number:
  US13/855,786
• Time in Patent Office: 496 Days
• Field of Search: 257/66
• US Class Current: 257/278
• CPC Class Codes: H01L 21/4871 Bases, plates or heatsinks
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/373 Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
• CPC Class Codes: H01L 23/3732 Diamonds
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/098 : the components being PN junction gate field-effect transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A 3D semiconductor device, including: a first layer including first transistors; a second layer including second transistors; where the second transistors are aligned to the first transistors, and a first circuit including at least one of the first transistors, where the first circuit has a first circuit output connected to at least one of the second transistors, and where at least one of the second transistors is connected to a device output, and where the device output includes a contact port for connection to external devices, and where at least one of the second transistors is substantially larger than at least one of the first transistors.

Claims

1. A 3D semiconductor device, comprising:

a first layer comprising first transistors;

a first metal layer comprising aluminum or copper overlaying said first transistors;

a second layer comprising second transistors;

wherein said second layer is overlying said first metal layer, and

wherein said second layer thickness is less than 200 nm,

a first circuit comprising at least one of said first transistors,

wherein said device comprises an Electro-Static-Discharge (“

ESD”

) protection structure connected to at least one input structure,

wherein said second layer comprises a first active portion of said ESD protection structure and said first layer comprises a second active portion of said ESD protection structure, and

wherein said least one input structure is adapted to connect an input to said device from an external device.

2. A 3D semiconductor device according to claim 1, further comprising:

a heat spreader layer disposed between said first layer and said second layer, and

a heat removal path extending from said heat spreader layer to a top or the bottom surface of said device.

3. A 3D semiconductor device according to claim 1,

wherein at least one of said second transistors comprises a back-bias region and

wherein said back-bias region is constructed from an electrically conductive material with a higher than 900°

C. melting temperature.

4. A 3D semiconductor device according to claim 1, further comprising:

a thermal connection path extending from said second layer to a top or bottom surface of said device

wherein a portion of said thermal connection path is designed to remove heat directly from at least one of said second transistors.

5. A 3D semiconductor device according to claim 1, further comprising:

a first power distribution grid to provide power to said first transistors; and

a second power distribution grid overlaying said second transistors,

wherein said second power distribution grid has a significantly larger current carrying capacity than said first power distribution grid.

6. A 3D semiconductor device according to claim 1, further comprising:

a power distribution network to provide power to said second transistors,

a heat removal path extending from said power distribution network to a top or bottom surface of said device.

7. A 3D semiconductor device according to claim 1, further comprising:

at least one thermally conductive and electrically non-conducting contact to said second layer to provide a heat removal path to at least one of said second transistors.

8. A 3D semiconductor device, comprising:

a first layer comprising first transistors;

a second layer comprising second transistors;

wherein said second layer is overlying said first transistors, and

wherein said second layer thickness is less than 200 nm, and

wherein said second transistors are lithographically defined with less than 10 nm alignment error to said first transistors, and

wherein said device comprises an Electro-Static-Discharge (“

ESD”

) protection structure connected to at least one input structure,

wherein said second layer comprises a first active portion of said ESD protection structure and said first layer comprises a second active portion of said ESD protection structure, and

wherein said least one input structure is adapted to connect an input to said device from an external device.

9. A 3D semiconductor device according to claim 8, further comprising:

a first power distribution grid to provide power to said first transistors; and

a second power distribution grid overlaying said second transistors,

wherein said second power distribution grid has a significantly larger current carrying capacity than said first power distribution grid.

10. A 3D semiconductor device according to claim 8, further comprising:

a heat removal structure designed to remove heat from at least one of said second transistors; and

at least one through second layer via,

wherein said heat removal structure comprises said at least one through second layer via.

11. A 3D semiconductor device according to claim 8,

wherein at least one of said second transistors comprises a back-bias region and

wherein said back-bias region is constructed from an electrically conductive material with a higher than 900°

C. melting temperature.

12. A 3D semiconductor device according to claim 8, further comprising:

a thermal connection path extending from said second layer to a top or bottom surface of said device

wherein a portion of said thermal connection path is in direct contact with said second layer and is designed to remove heat directly from at least one of said second transistors.

13. A 3D semiconductor device according to claim 8, further comprising:

a power distribution network to provide power to said second transistors, and

a heat removal path extending from said power distribution network to a top or bottom surface of said device.

14. A 3D semiconductor device according to claim 8, further comprising:

a heat spreader layer disposed between said first layer and said second layer, and

a heat removal path extending from said heat spreader layer to a top or the bottom surface of said device.

15. A 3D semiconductor device according to claim 8, further comprising:

at least one thermally conductive and electrically non-conducting contact to said second layer to provide a heat removal path to at least one of said second transistors.

16. A 3D semiconductor device, comprising:

a first layer comprising first transistors;

a first metal layer comprising aluminum or copper overlaying said first transistors; and

a second layer comprising second transistors;

wherein said second layer is overlying said first metal layer, and

wherein said second layer thickness is less than 200 nm, and

wherein said second transistors are lithographically defined with less than 10 nm alignment error to said first transistors, and

wherein said device comprises an Electro-Static-Discharge (“

ESD”

) protection structure connected to at least one input structure,

wherein said second layer comprises a first active portion of said ESD protection structure and said first layer comprises a second active portion of said ESD protection structure, and

wherein said least one input structure is adapted to connect an input to said device from an external device.

17. A 3D semiconductor device according to claim 16, further comprising:

at least one thermally conductive and electrically non-conducting contact to said second layer to provide a heat removal path to at least one of said second transistors.

18. A 3D semiconductor device according to claim 16,

wherein at least one of said second transistors comprises a back-bias region and

wherein said back-bias region is constructed from an electrically conductive material with higher than 900°

C. melting temperature.

19. A 3D semiconductor device according to claim 16, further comprising:

a thermal connection path for at least one of said second transistors extending from said second layer to a top or bottom surface of said device

wherein a portion of said thermal connection path is in direct contact with said second layer.

20. A 3D semiconductor device according to claim 16, further comprising:

a first power distribution grid to provide power to said first transistors; and

a second power distribution grid overlaying said second transistors,

wherein said second power distribution grid has a significantly larger current carrying capacity than said first power distribution grid.

21. A 3D semiconductor device according to claim 16, further comprising:

a heat spreader layer disposed between said first layer and said second layer, and

a heat removal path extending from said heat spreader layer to a top or the bottom surface of said device.

22. 3D semiconductor device according to claim 16, further comprising:

a power distribution network to provide power to said second transistors, and

a heat removal path extending from said power distribution network to a top or bottom surface of said device.

23. A 3D semiconductor device, comprising:

a first layer comprising first transistors;

a first metal layer comprising aluminum or copper overlaying said first transistors; and

a second layer comprising second transistors;

wherein said second layer is overlying said first metal layer, and

wherein said second layer thickness is less than 200 nm, and

wherein said device comprises an Electro-Static-Discharge (“

ESD”

) protection structure connected to at least one input structure, and

wherein said second layer comprises a first active portion of said ESD protection structure, and said first layer comprises a second active portion of said ESD protection structure, and

wherein said least one input structure is adapted to connect an input to said device from an external device, and

wherein said first layer comprises at least one first circuit comprising said first transistors, said at least one first circuit is circumscribed by a first guard ring, and

wherein said second layer comprises at least one second circuit comprising said second transistors, said at least one second circuit is circumscribed by a second guard ring, and

wherein said second guard ring overlays said first guard ring.

24. 3D semiconductor device according to claim 23, further comprising:

a heat removal structure designed to remove heat from at least one of said second transistors; and

at least one through second layer via,

wherein said heat removal structure comprises said at least one through second layer via.

25. 3D semiconductor device according to claim 23,

wherein at least one of said second transistors comprises a back-bias region and

wherein said back-bias region is constructed from an electrically conductive material with higher than 900°

C. melting temperature.

26. 3D semiconductor device according to claim 23, further comprising:

a thermal connection path extending from said second layer to a top or bottom surface of said device

wherein a portion of said thermal connection path is in direct contact with said second layer and is designed to provide a heat removal path directly from at least one of said second transistors.

27. 3D semiconductor device according to claim 23, further comprising:

a heat-spreader layer disposed between said first layer and said second layer; and

a heat removal path extending from said heat spreader layer to a top or the bottom surface of said device.

28. 3D semiconductor device according to claim 23, further comprising:

a first power distribution grid to provide power to said first transistors; and

a second power distribution grid overlaying said second transistors,

wherein said second power distribution grid has significantly larger current carrying capacity than said first power distribution grid.

29. 3D semiconductor device according to claim 23, further comprising:

a power distribution network to provide power to said second transistors, and

a heat removal path extending from said power distribution network to a top or bottom of said device.

30. 3D semiconductor device according to claim 23, further comprising:

at least one thermally conductive and electrically non-conducting contact to said second layer to provide a heat removal path to at least one of said second transistors.