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Shielded gate field effect transistors

  • US 8,803,207 B2
  • Filed: 04/06/2011
  • Issued: 08/12/2014
  • Est. Priority Date: 06/29/2005
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a trench disposed in a semiconductor region;

    a shield dielectric layer lining a lower portion of a sidewall of the trench and a bottom surface of the trench;

    a gate dielectric lining a upper portion of the sidewall of the trench;

    a shield electrode disposed in a lower portion of the trench and insulated from the semiconductor region by the shield dielectric layer;

    an inter-electrode dielectric (IED) disposed in the trench over the shield electrode, the shield electrode having a curved top surface; and

    a gate electrode disposed in an upper portion of the trench, the gate electrode being insulated from the shield electrode by the IED, the gate electrode having a first protrusion, a second protrusion, and a third protrusion, the second protrusion of the gate electrode being aligned along a centerline, the gate electrode having a bottom surface defining a first notch disposed on a first side of the centerline between the first protrusion and the second protrusion and a second notch disposed on a second side of the centerline between the second protrusion and the third protrusion.

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