Shielded gate field effect transistors

• US 8,803,207 B2
• Filed: 04/06/2011
• Issued: 08/12/2014
• Est. Priority Date: 06/29/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Grebs, Thomas E., Kraft, Nathan Lawrence, Ridley, Rodney, Dolny, Gary M., Yedinak, Joseph A., Kocon, Christopher Boguslaw, Challa, Ashok
• Primary Examiner(s): Ahmadi, Mohsen
• Application Number:
  US13/081,400
• Publication Number:
  US 20110212586A1
• Time in Patent Office: 1,224 Days
• Field of Search: 257/288, 257/330, 257/332, 257/334, 257/E21.19, 257/E21.548, 257/E21.549
• US Class Current: 257/288
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one general aspect, an apparatus can include a trench disposed in a semiconductor region, a shield dielectric layer lining a lower portion of a sidewall of the trench and a bottom surface of the trench, and a gate dielectric lining a upper portion of the sidewall of the trench. The apparatus can also include a shield electrode disposed in a lower portion of the trench and insulated from the semiconductor region by the shield dielectric layer, and an inter-electrode dielectric (IED) disposed in the trench over the shield electrode where the shield electrode has a curved top surface.

Claims

1. An apparatus, comprising:

a trench disposed in a semiconductor region;

a shield dielectric layer lining a lower portion of a sidewall of the trench and a bottom surface of the trench;

a gate dielectric lining a upper portion of the sidewall of the trench;

a shield electrode disposed in a lower portion of the trench and insulated from the semiconductor region by the shield dielectric layer;

an inter-electrode dielectric (IED) disposed in the trench over the shield electrode, the shield electrode having a curved top surface; and

a gate electrode disposed in an upper portion of the trench, the gate electrode being insulated from the shield electrode by the IED, the gate electrode having a first protrusion, a second protrusion, and a third protrusion, the second protrusion of the gate electrode being aligned along a centerline, the gate electrode having a bottom surface defining a first notch disposed on a first side of the centerline between the first protrusion and the second protrusion and a second notch disposed on a second side of the centerline between the second protrusion and the third protrusion.

2. The apparatus of claim 1, wherein the semiconductor region has a first conductivity type, the apparatus further comprising:

a body region of a second conductivity type disposed in the semiconductor region; and

a source region of the first conductivity type disposed in the body region and flanking the trench.

3. The apparatus of claim 1, wherein the semiconductor region includes a mesa region adjacent the trench, the mesa region including a recessed portion having a bottom surface below a top surface of the gate electrode.

4. The apparatus of claim 1, wherein the inter-electrode dielectric includes a first portion disposed within the first notch and a second portion disposed within the second notch.

5. The apparatus of claim 1, wherein at least a portion of the trench has a tapered shape.

6. The apparatus of claim 1 wherein the gate has a thickness less than a thickness of the inter-electrode dielectric.

7. The apparatus of claim 1, wherein the gate electrode has a top surface at a depth that is recessed relative to a top of the trench.

8. The apparatus of claim 1, wherein each of the first notch and the second notch defines a recess curving in a same direction as the top surface of the shield electrode.

9. The apparatus of claim 1, wherein the curved top surface of the shield electrode protrudes into the inter-electrode dielectric.

10. The apparatus of claim 1, wherein the semiconductor region includes silicon carbide.

11. An apparatus, comprising:

a trench disposed in a semiconductor region of a first conductivity type;

a shield electrode disposed in a lower portion of the trench, the shield electrode being insulated from the semiconductor region by a shield dielectric, the shield electrode having a curved top surface;

a gate electrode disposed in the trench above the shield electrode, the gate electrode being insulated from the semiconductor region by a gate dielectric, the gate electrode having a bottom surface defining a plurality of protrusions including a first protrusion, a second protrusion, and a third protrusion, the second protrusion of the gate electrode being aligned along a centerline,

the gate electrode having a bottom surface defining a first notch disposed on a first side of the centerline between the first protrusion and the second protrusion and a second notch disposed on a second side of the centerline between the second protrusion and the third protrusion;

an inter-electrode dielectric disposed between the shield electrode and the gate electrode;

a mesa adjacent the trench; and

a region of a second conductivity disposed in the mesa and disposed above the semiconductor region of the first conductivity type.

12. The apparatus of claim 11, wherein a portion of the trench disposed around the shield electrode has a width narrower than a width of a portion of the trench disposed around the gate electrode, the shield electrode has a width less than a width of the gate electrode.

13. The apparatus of claim 11, wherein the inter-electrode dielectric includes a portion disposed within the first notch.

14. The apparatus of claim 11, wherein the mesa has a recessed portion.

15. The apparatus of claim 11, wherein the gate dielectric has a thickness less than a thickness of the inter-electrode dielectric.

16. The apparatus of claim 11, wherein the gate electrode has a top surface at a depth that is recessed relative to a top surface of the mesa.

17. The apparatus claim 11, wherein the semiconductor region includes silicon carbide.

18. An apparatus, comprising:

a trench disposed in a semiconductor region, at least a portion of the trench has a tapered shape;

a shield electrode disposed in a lower portion of the trench, the shield electrode being insulated from the semiconductor region by a shield dielectric;

a gate electrode disposed in the trench above the shield electrode and aligned along a centerline, a portion of the trench disposed around the shield electrode having a width narrower than a width of a portion of the trench disposed around the gate electrode, the gate electrode having a bottom surface defining a plurality of notches and a plurality of protrusions, the plurality of notches including a first notch disposed between a first pair of protrusions from the plurality of protrusions, and including a second notch disposed between a second pair of protrusions from the plurality of protrusions, the first notch being disposed on a first side of the centerline and the second notch being disposed on a second side of the centerline;

an inter-electrode dielectric disposed between the shield electrode and the gate electrode;

a mesa disposed adjacent the trench and having a recessed portion; and

a gate dielectric formed along a sidewall of an upper portion of the trench, the gate dielectric having a thickness less than a thickness of the inter-electrode dielectric.

19. The apparatus of claim 18, wherein the gate electrode has a top surface at a depth that is recessed relative to a top of the trench.

20. The apparatus of claim 18, wherein the semiconductor region includes silicon carbide.