Three dimensional memory and methods of forming the same

• US 8,803,214 B2
• Filed: 06/28/2010
• Issued: 08/12/2014
• Est. Priority Date: 06/28/2010
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tang, Sanh D., Zahurak, John K.
• Primary Examiner(s): Chaudhur, Olik
• Assistant Examiner(s): JEAN BAPTISTE, WILNER
• Application Number:
  US12/825,211
• Publication Number:
  US 20110316063A1
• Time in Patent Office: 1,506 Days
• Field of Search: 257/314, 257/E21.602, 257/E29.255, 257/E21.001, 438/128, 438/309, 365/189.11
• US Class Current: 257/314
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/10 : characterised by the top-view layout
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 : characterised by the boundary region between the core and peripheral circuit regions
• CPC Class Codes: H10B 63/34 : of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/231 : based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect

Abstract

Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

Claims

1. An apparatus comprising:

a substrate of a memory device;

a plurality of first memory cells located in a first device level of the memory device over the substrate;

a plurality of second memory cells located in a second device level of the memory device over the first device level and over the substrate, wherein the first device level is different from the second device level;

a first control gate formed in the first device level, the first control gate to control access to the first memory cells, wherein each of the first memory cells includes a memory element formed in a cavity of the first control gate;

a second control gate formed in the second device level, the second control gate to control access to the second memory cells, wherein each of the second memory cells includes a memory element formed in a cavity of the second control gate; and

data lines configured to be selectively coupled to a common source and the memory cells through conductive material.

2. The apparatus of claim 1, wherein the first and second memory cells include multiple memory cells arranged in a first direction and multiple memory cells arranged in a second direction,

the conductive material extending through the first and second memory cells in a third direction, the third direction being substantially perpendicular to the first and second directions.

3. The apparatus of claim 2, wherein the common source is formed over a substrate of the memory device, such that the common source is between the first and second memory cells and the substrate to allow electrons from the memory element of at least one of the first and second memory cells to move to the common source during an erase operation.

4. The apparatus of claim 1, wherein the first memory cells are substantially vertically aligned with the second memory cells.

5. The apparatus of claim 1, wherein the memory element of each of the first memory cells is substantially vertically aligned with the memory element of one of the second memory cells.

6. The apparatus of claim 1, further comprising transistors to selectively couple the first and second memory cells to the data lines associated with the first and second memory cells during a memory operation of the memory device, wherein at least one of the transistors comprises a double-gate.

7. The apparatus of claim 1, further comprising transistors to selectively couple the first and second memory cells to the data lines associated with the first and second memory cells during a memory operation of the memory device, wherein at least one of the transistors comprises a surrounded gate.

8. An apparatus comprising:

a plurality of first memory cells located in a first device level of a memory device;

a plurality of second memory cells located in a second device level of the memory device;

a first control gate formed in the first device level, the first control gate to control access to the first memory cells, wherein each of the first memory cells includes a memory element formed in a cavity of the first control gate;

a second control gate formed in the second device level, the second control gate to control access to the second memory cells, wherein each of the second memory cells includes a memory element formed in a cavity of the second control gate, wherein the first and second memory cells include multiple memory cells arranged in a first direction and multiple memory cells arranged in a second direction;

a common source; and

data lines configured to be selectively coupled to the common source and the first and second memory cells through conductive material, the conductive material extending through the first and second memory cells in a third direction, the third direction being substantially perpendicular to the first and second directions, wherein the common source is formed over a substrate of the memory device, such that the first and second memory cells are between the common source and the substrate.

9. An apparatus comprising:

a first non-volatile memory cell including a first memory element, the first memory element having a ring shape, the first memory element located in a first device level of a memory device;

a second non-volatile memory cell including a second memory element, the second memory element having a ring shape, the second memory element located in a second device level of the memory device, wherein the first device level is different from the second device level;

a conductive material extending through the first and second memory elements; and

a data line configured to be selectively coupled to a common source and the first and second memory cells through the conductive material.

10. The apparatus of claim 9, further comprising:

a first additional conductive material configured to operate as a control gate to access the first memory cell, wherein the first memory element and the first additional conductive material are located in the first device level of the memory device; and

a second additional conductive material configured to operate as a control gate to access the second memory cell, wherein the second memory element and the second additional conductive material are located in the second device level of the memory device.

11. The apparatus of claim 10, wherein each of the first and second memory cells further includes a first dielectric between the respective memory element and the conductive material.

12. The apparatus of claim 11, wherein each of the first and second memory cells further includes a second dielectric between the respective memory element and the respective additional conductive material.

13. The apparatus of claim 9, wherein the data line is located between the substrate and the first memory cell.

14. The apparatus of claim 9, wherein the first and second memory cells are located between the substrate and the data line.

15. An apparatus comprising:

a substrate of a memory device;

a first conductive material located in a first device level of the memory device over the substrate, the first conductive material including a first cavity, the first cavity having a first sidewall;

a second conductive material located in a second device level of the memory device over the first device level and over the substrate, the second conductive material including a second cavity, the second cavity having a second sidewall, wherein the first device level is different from the second device level;

a first dielectric formed on the first sidewall and the second sidewall;

a first memory element located in the first cavity and electrically isolated from the first conductive material by a first portion of the first dielectric;

a second memory element located in the second cavity and electrically isolated from the second conductive material by a second portion of the first dielectric;

a second dielectric formed on a side of the first memory element and on a side of the second memory element; and

a conductive channel extending from the first device level to the second device level and facing the first and second memory elements, such that the conductive channel is electrically isolated from the first and second memory elements by at least a respective portion of the second dielectric.

16. The apparatus of claim 15, wherein the first and second memory elements comprise polysilicon.

17. The apparatus of claim 15, wherein the first and second memory elements comprise a dielectric material.

18. The apparatus of claim 17, wherein the dielectric material comprises silicon nitride.

19. The apparatus of claim 15, further comprising dielectric material between the first and second conductive materials.

20. The apparatus of claim 15, further comprising:

a data line configured to be selectively coupled to the conductive channel, wherein the first and second memory elements are located between the data line and the substrate.

21. An apparatus comprising:

a first conductive material located in a first device level of a memory device, the first conductive material including a first cavity, the first cavity having a first sidewall;

a second conductive material located in a second device level of the memory device, the second conductive material including a second cavity, the second cavity having a second sidewall;

a first dielectric formed on the first sidewall and the second sidewall;

a first memory element located in the first cavity and electrically isolated from the first conductive material by a first portion of the first dielectric;

a second memory element located in the second cavity and electrically isolated from the second conductive material by a second portion of the first dielectric;

a second dielectric formed on a side of the first memory element and on a side of the second memory element;

a conductive channel extending from the first device level to the second device level and facing the first and second memory elements, such that the conductive channel is electrically isolated from the first and second memory elements by at least a respective portion of the second dielectric;

a substrate; and

a data line configured to be selectively coupled to the conductive channel, wherein the data line is located between the second conductive material and the substrate.