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Three-dimensional semiconductor memory devices using direct strapping line connections

  • US 8,803,222 B2
  • Filed: 07/06/2012
  • Issued: 08/12/2014
  • Est. Priority Date: 07/07/2011
  • Status: Active Grant
First Claim
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1. A memory device, comprising:

  • a plurality of gate stacks extending in parallel on a substrate along a first direction;

    a plurality of insulation regions extending along the first direction and respectively disposed between adjacent ones of the gate stacks, the insulation regions having linear first portions having a first width and widened second portions having a second width greater than the first width;

    a common source region in the substrate underlying the at least one insulation region;

    respective conductive plugs passing through respective ones of the widened second portions of the insulation regions and electrically connected to the common source region; and

    a plurality of strapping lines disposed on the conductive plugs and extending along the first direction, respectively disposed between the adjacent ones of the gate stacks and in direct contact with the conductive plugs.

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