Three-dimensional semiconductor memory devices using direct strapping line connections

• US 8,803,222 B2
• Filed: 07/06/2012
• Issued: 08/12/2014
• Est. Priority Date: 07/07/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Bongyong, Lee, Ae-Jeong, Kim, Dongchan, Kim, Sang-Hoon
• Primary Examiner(s): SHINGLETON, MICHAEL B
• Application Number:
  US13/543,312
• Publication Number:
  US 20130009236A1
• Time in Patent Office: 767 Days
• Field of Search: 257/324, 257/E29.309, 257/E29.262
• US Class Current: 257/324
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Memory devices include a plurality of elongate gate stacks extending in parallel on a substrate and at least one insulation region disposed in a trench between adjacent ones of the gate stacks. The at least one insulation region has linear first portions having a first width and widened second portions having a second width greater than the first width. A common source region is disposed in the substrate underlying the at least one insulation region. The devices further include respective conductive plugs passing through respective ones of the widened second portions of the at least one insulation region and electrically connected to the common source region and at least one strapping line disposed on the conductive plugs between the adjacent ones of the gate stacks and in direct contact with the conductive plugs.

Claims

1. A memory device, comprising:

a plurality of gate stacks extending in parallel on a substrate along a first direction;

a plurality of insulation regions extending along the first direction and respectively disposed between adjacent ones of the gate stacks, the insulation regions having linear first portions having a first width and widened second portions having a second width greater than the first width;

a common source region in the substrate underlying the at least one insulation region;

respective conductive plugs passing through respective ones of the widened second portions of the insulation regions and electrically connected to the common source region; and

a plurality of strapping lines disposed on the conductive plugs and extending along the first direction, respectively disposed between the adjacent ones of the gate stacks and in direct contact with the conductive plugs.

2. The device of claim 1, wherein each of the gate stacks comprises a plurality of vertical channel regions distributed along the first direction and wherein the plugs are spaced apart along the first direction.

3. The device of claim 2, further comprising at least one bit line electrically connected to the vertical channel regions and extending along a second direction perpendicular to the first direction, wherein top surfaces of the plugs are located at a level higher than top surfaces of the vertical channel regions and lower than the at least one bit line and the at least one strapping line.

4. The device of claim 3, further comprising a common source line electrically connected in common to the plurality of strapping lines.

5. The device of claim 4, wherein the common source line is disposed at the same level as the at least one bit line.

6. The device of claim 1, further comprising a barrier layer conforming to bottom and side surfaces of the at least one insulation region.

7. The device of claim 1, further comprising a plurality of bit lines electrically connected to the vertical channel regions and having bottom surfaces disposed at a level higher than top surfaces of the strapping lines.

8. The device of claim 7, wherein the bit lines extend along a second direction perpendicular to the first direction and cross over the strapping lines.

9. A memory device, comprising:

a plurality of gate stacks extending in parallel on a substrate along a first direction, each of the gate stacks comprising a plurality of vertical channel regions;

a plurality of insulation regions extending along the first direction and respectively disposed between adjacent ones of the gate stacks, the insulation regions having linear first portions having a first width and widened second portions having a second width greater than the first width;

a common source region in the substrate underlying the insulation regions;

respective conductive plugs passing through respective ones of the widened second portions of the insulation regions and electrically connected to the common source region;

at least one bit line electrically connected to the vertical channel regions; and

a plurality of strapping lines disposed on the conductive plugs and extending along the first direction, respectively disposed between the adjacent ones of the gate stacks,

wherein top surfaces of the conducive plugs are located at a level higher than top surfaces of the vertical channel regions and lower than the at least one bit line.

10. The device of claim 9, further comprising a common source line electrically connected in common to the plurality of strapping lines, wherein the common source line is disposed at the same level as the at least one bit line.

11. The device of claim 9, wherein the at least one bit line extends along a second direction perpendicular to the first direction and cross over the strapping lines.