Vertical mirror in a silicon photonic circuit

• US 8,803,268 B2
• Filed: 04/26/2013
• Issued: 08/12/2014
• Est. Priority Date: 09/25/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Heck, John, Liu, Ansheng, Morse, Michael T., Rong, Haisheng
• Primary Examiner(s): GEBREMARIAM, SAMUEL A
• Application Number:
  US13/871,083
• Publication Number:
  US 20130299932A1
• Time in Patent Office: 473 Days
• Field of Search: 257/431, 257/290, 257/443, 257/459
• US Class Current: 257/431
• CPC Class Codes: G02B 6/4214 the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device G02B6/4246 takes precedence
• CPC Class Codes: H01L 31/02327 the optical elements being integrated or being directly associated to the device, e.g. back reflectors optical coatings H01L31/0216

Abstract

A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing.

Claims

1. A vertical mirror on a silicon photonic circuit, comprising:

a silicon device wafer;

a buried oxide (BOX) layer under the silicon device wafer;

a handle wafer doped with a p-type dopant under the BOX layer; and

a trapezoid shaped area having a bottom side defined by the handle wafer, opposite vertical sides defined by the BOX layer, and inwardly angled facets above the vertical sides defined by the silicon device wafer, wherein the facets act as vertical total internal reflection (TIR) mirrors.

2. The vertical mirror as recited in claim 1, further comprising:

an oxide layer filling the trapezoid shaped area.

3. The vertical mirror as recited in claim 2, wherein the surface of the silicon device wafer has a (100) crystal plane orientation.

4. The vertical mirror as recited in claim 1 wherein the facet lies in a (111) crystal plane orientation in the silicon device wafer.

5. The vertical mirror as recited in claim 1 wherein the P-type dopant comprises boron having a concentration of approximately 1020 cm-3.

6. The vertical mirror as recited in claim 1 wherein the facet comprises an angle 54 degrees to 45 degrees to the normal.

7. The vertical mirror as recited in claim 6 further comprising a Ge photodetector over the facet having a mirror formed on top of the photodetector to cause light to pass through the Ge photodetector twice.