Through-substrate vias and methods for forming the same

• US 8,803,292 B2
• Filed: 04/27/2012
• Issued: 08/12/2014
• Est. Priority Date: 04/27/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ming-Fa, Wang, Yu-Young, Jan, Sen-Bor
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): Smith, Stephen C
• Application Number:
  US13/457,823
• Publication Number:
  US 20130285125A1
• Time in Patent Office: 837 Days
• Field of Search: 257/621, 257/773, 257/774, 438/667
• US Class Current: 257/621
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A device includes a semiconductor substrate and a Metal-Oxide-Semiconductor (MOS) transistor. The MOS transistor includes a gate electrode over the semiconductor substrate, and a source/drain region on a side of the gate electrode. A source/drain contact plug includes a lower portion and an upper portion over the lower portion, wherein the source/drain contact plug is disposed over and electrically connected to the source/drain region. A gate contact plug is disposed over and electrically connected to the gate electrode, wherein a top surface of the gate contact plug is level with a top surface of the top portion of the source/drain contact plug. A Through-Substrate Via (TSV) extends into the semiconductor substrate. A top surface of the TSV is substantially level with an interface between the gate contact plug and the gate electrode.

Claims

1. A device comprising:

a semiconductor substrate;

a Metal-Oxide-Semiconductor (MOS) transistor comprising;

a gate electrode over the semiconductor substrate; and

a source/drain region on a side of the gate electrode;

a source/drain contact plug comprising a lower portion and an upper portion over the lower portion, wherein the source/drain contact plug is over and electrically connected to the source/drain region;

a gate contact plug over and electrically connected to the gate electrode, wherein a top surface of the gate contact plug is level with a top surface of the upper portion of the source/drain contact plug; and

a Through-Substrate Via (TSV) extending into the semiconductor substrate, wherein a top surface of the TSV is level with an interface between the gate contact plug and the gate electrode.

2. The device of claim 1 further comprising:

an inter-layer dielectric over the semiconductor substrate, wherein the gate electrode and the lower portion of the source/drain contact plug comprise portions in the inter-layer dielectric; and

an etch stop layer over and contacting the inter-layer dielectric, wherein the top surface of the TSV is in contact with the etch stop layer.

3. The device of claim 2, wherein the gate contact plug and the upper portion of the source/drain contact plug penetrate through the etch stop layer.

4. The device of claim 1 further comprising a via and a metal line over the via, wherein the via and the metal line form a dual damascene structure, and wherein a bottom surface of the via is in contact with a top surface of the gate contact plug.

5. The device of claim 4 further comprising:

an inter-layer dielectric over the gate electrode, wherein the upper portion of the source/drain contact plug comprises a portion disposed in the inter-layer dielectric; and

an etch stop layer over the inter-layer dielectric, wherein the via extends into the etch stop layer.

6. The device of claim 1, wherein the upper portion and the lower portion of the source/drain contact plug have a distinguishable interface.

7. The device of claim 1 further comprising a TSV contact plug over and contacting the TSV, wherein the TSV contact plug is at a same level as the gate contact plug.

8. The device of claim 1, wherein the TSV comprises:

an insulation layer in contact with the semiconductor substrate;

a diffusion barrier layer over the insulation layer; and

a metallic material over the diffusion barrier layer, wherein each of the insulation layer, the diffusion barrier layer, and the metallic material extend from the interface into the semiconductor substrate.