TSV structures and methods for forming the same

• US 8,803,316 B2
• Filed: 12/06/2011
• Issued: 08/12/2014
• Est. Priority Date: 12/06/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Yung-Chi, Chen, Hsin-Yu, Chiou, Wen-Chih, Yang, Ku-Feng, Wu, Tsang-Jiuh, Lin, Jing-Cheng
• Primary Examiner(s): Trinh, Hoa B
• Application Number:
  US13/311,692
• Publication Number:
  US 20130140690A1
• Time in Patent Office: 980 Days
• Field of Search: 257685-686, 257/737, 257 77-784
• US Class Current: 257/737
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/11011 Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/1405 Shape
• CPC Class Codes: H01L 2224/14104 relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/067 : Polyphenylene
• CPC Class Codes: H01L 2924/0705 : Sulfur containing polymer
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.

Claims

1. A device comprising:

a substrate comprising a front side and a backside;

a through-via extending from the backside to the front side of the substrate;

a conductive pad on the backside of the substrate and over the through-via, wherein the conductive pad comprises a substantially planar top surface; and

a conductive bump having a non-planar top surface over the substantially planar top surface and aligned to the through-via, wherein the conductive bump and the conductive pad are formed of a same material, and wherein no interface is formed between the conductive bump and the conductive pad.

2. The device of claim 1, wherein the top surface of the conductive bump is rounded.

3. The device of claim 1, wherein the conductive bump has a height between about 0.1 μ

m and about 10 μ

m.

4. The device of claim 1, wherein the conductive bump has a lateral dimension between about 2.0 μ

m and about 30 μ

m.

5. The device of claim 1, wherein the substantially planar top surface is aligned to a portion of the substrate encircling the through-via.

6. The device of claim 1 further comprising a metal-oxide-semiconductor (MOS) device on the front side of the substrate.

7. The device of claim 1 further comprising an under-bump metallurgy (UBM) over the conductive bump and the conductive pad, wherein the UBM comprises a first portion over and in contact with the non-planar top surface of the conductive bump, and a second portion over and in contact with the substantially planar top surface of the conductive pad.

8. The device of claim 1 further comprising a solder region over the conductive pad and the conductive bump, wherein the solder region comprises a first bottom surface that is not planar, and a second bottom surface that is substantially planar, and wherein the first bottom surface is higher than the second bottom surface.

9. The device of claim 8 further comprising a passivation layer on the backside of the substrate, wherein the passivation layer comprises portions covering edge portions of the conductive pad, and wherein the solder region is electrically coupled to the conductive bump and the conductive pad through an opening in the passivation layer.

10. The device of claim 9 further comprising a stress buffer layer over the passivation layer and on the backside of the substrate, wherein the stress buffer layer comprises portions covering the edge portions of the conductive pad, and wherein the solder region is electrically coupled to the conductive bump and the conductive pad through an opening in the stress buffer layer.

11. The device of claim 10, wherein the stress buffer layer is underlying and aligned to the solder region, and does not extend beyond the solder region.

12. A device comprising:

a semiconductor substrate comprising a front side and a backside;

a through-via extending from the backside to the front side of the semiconductor substrate;

a metal connector on the backside of the semiconductor substrate and over the through-via, wherein the metal connector comprises;

a substantially planar top surface; and

a non-planar top surface smoothly connected to the substantially planar top surface; and

a metal feature over and in contact with the substantially planar top surface and the non-planar top surface of the metal connector, wherein the metal feature and the metal connector comprise different materials.

13. The device of claim 12, wherein the metal connector and the through-via are formed of a same material, and wherein no visible interface is formed between the through-via and the metal connector.

14. The device of claim 12, wherein the non-planar top surface of the metal connector is higher than the substantially planar top surface by greater than about 0.1 μ

m.

15. The device of claim 12, wherein the metal feature comprises:

a nickel-containing layer in contact with the metal connector, wherein the nickel-containing layer comprises a non-planar portion aligned to the through-via, and a planar portion not aligned to the through-via; and

a solder region over the nickel-containing layer, wherein the solder region comprises a non-planar bottom surface portion aligned to the through-via, and a planar bottom surface portion not aligned to the through-via.

16. A device comprising:

a substrate comprising a front side and a backside;

a through-substrate via (TSV) extending from the front side to the backside of the substrate;

a first metal feature on the backside of the substrate and over the TSV relative the backside of the substrate, wherein the first metal feature has a first portion having a substantially planar top surface and a second portion over the first portion relative the backside of the substrate, the second portion having a non-planar top surface; and

a second metal feature over and contacting the first metal feature relative the backside, wherein the first and second metal features are formed of different materials.

17. The device of claim 16, further comprising a metal line over the top surface of the substrate relative the top side of the substrate, wherein the TSV is connected to the metal line.

18. The device of claim 16, further comprising a liner covering at least a portion of the backside of the substrate and sidewalls of the TSV.

19. The device of claim 16, wherein the TSV and the first metal feature are formed of a same material and form an uninterrupted metallic region.

20. The device of claim 16, wherein the top surface of the second portion of the first metal feature is substantially rounded.