Reconfigurable sequencer structure

• US 8,803,552 B2
• Filed: 09/25/2012
• Issued: 08/12/2014
• Est. Priority Date: 09/06/2002
• Status: Expired due to Term

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Pact XPP Technologies, AG
• Inventors: Vorbach, Martin
• Primary Examiner(s): LE, DON P
• Application Number:
  US13/626,047
• Publication Number:
  US 20130024657A1
• Time in Patent Office: 686 Days
• Field of Search: 326 37- 41, 326/46
• US Class Current: 326/38
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components

Abstract

A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory cell means.

Claims

1. A data processor chip comprising:

a plurality of data processing elements each including at least one arithmetic-logic-unit;

a plurality of memory elements adapted for storing at least one of program data and program code;

at least one input/output element adapted for transmitting data to and receiving data from at least one of a high level memory and peripherals; and

a bus system;

wherein;

each of the data processing, memory, and input/output elements is dedicated to its respective function and separate from each other;

the bus system interconnects the data processing, memory, and input/output elements for transmitting data between specific ones of the elements according to a setting of the bus system at runtime; and

each of the data processing, memory, and input/output elements is flexibly connectable for transmitting data to at least one other of the data processing, memory, and input/output elements depending on the setting of the bus system at runtime.

2. A data processor chip comprising:

a plurality of data processing elements each including at least one arithmetic-logic unit;

a plurality of memory elements adapted for storing at least one of program data and program code;

at least one input/output element adapted for transmitting data to and receiving data from at least one of a high level memory and peripherals; and

a bus system;

wherein each of the data processing, memory, and input/output elements is dedicated to its respective function and separate from each other;

the bus system interconnects the data processing, memory, and input/output elements for transmitting data between specific ones of the elements according to a setting of the bus system; and

each of the data processing, memory, and input/output elements is adapted for transmitting data to at least one other of the data processing, memory, and input/output elements depending on the setting of the bus system.

3. A computer system including:

a data processor chip having a plurality of data processing elements each including at least one arithmetic-logic unit;

a plurality of memory elements adapted for storing at least one of program data and program code;

at least one input/output element adapted for transmitting data to and receiving data from at least one of a high level memory and peripherals; and

a bus system;

wherein each of the data processing, memory, and input/output elements is dedicated to its respective function and separate from each other;

the bus system interconnects the data processing, memory, and input/output elements for transmitting data between specific ones of the elements according to a setting of the bus system; and

each of the data processing, memory, and input/output elements is adapted for transmitting data to at least one other of the data processing, memory, and input/output elements depending on the setting of the bus system.

4. A computer system including:

a plurality of data processing elements each including an arithmetic-logic unit;

a plurality of memory elements adapted for storing at least one of program data and program code;

at least one input/output element adapted for transmitting data to and receiving data from at least one of a high level memory and peripherals; and

a bus system;

wherein each of the data processing, memory, and input/output elements is separate from the others of the data processing, memory and input/output elements, and each of the data processing, memory, and input/output elements is adapted specifically to perform respectively the functions of data processing, memory storage, and input/output; and

the bus system interconnects the data processing, memory, and input/output elements such that specific pairs of the elements are interconnected depending upon a setting of the bus system.