Solid-state imaging device

• US 8,803,598 B2
• Filed: 02/21/2013
• Issued: 08/12/2014
• Est. Priority Date: 07/12/2012
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sato, Eiji
• Primary Examiner(s): Zweizig, Jeffrey
• Application Number:
  US13/773,318
• Publication Number:
  US 20140015600A1
• Time in Patent Office: 537 Days
• Field of Search: 327/514, 327/515, 327/534, 327/564, 327/565
• US Class Current: 327/565
• CPC Class Codes: G05F 3/02 Regulating voltage or current
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 31/0224 Electrodes

Abstract

A semiconductor element layer has a pixel region in which a plurality of photodiodes are provided and a peripheral circuit region in which a peripheral circuit for processing the device is provided, a power supply line to supply an electric power to the peripheral circuit, provided at a first side of the semiconductor element layer in the peripheral circuit region, a first wiring layer to supply the electric power to the power supply line, provided at a second side of the semiconductor element layer in the peripheral circuit region, and a plurality of first through-electrodes, provided in the peripheral circuit region and passing through the semiconductor element layer between the first side and the second side. At least a part of the first through-electrodes electrically connect between the power supply line and the first wiring layer.

Claims

1. A solid-state imaging device, comprising:

a semiconductor element layer having a pixel region in which a plurality of photodiodes are provided and a peripheral circuit region in which a peripheral circuit for processing of signals generated from the pixels is provided;

a power supply line to supply an electric power to the peripheral circuit, provided at a first side of the semiconductor element layer in the peripheral circuit region;

a first wiring layer to supply the electric power to the power supply line, provided at a second side of the semiconductor element layer in the peripheral circuit region; and

a plurality of first through-electrodes, provided in the peripheral circuit region and passing through the semiconductor element layer between the first side and the second side,

wherein at least a part of the first through-electrodes electrically connect between the power supply line and the first wiring layer.

2. The solid-state imaging device according to claim 1, wherein

the first through-electrodes are arrayed in the peripheral circuit region at a predetermined distance.

3. The solid-state imaging device according to claim 2, wherein

at least one of the first through-electrodes are electrically connected to the power supply line at the first side and electrically insulated from the first wiring layer at the second side.

4. The solid-state imaging device according to claim 3, wherein

the first through-electrodes that electrically connected to the power supply line at the first side and electrically insulated from the first wiring layer at the second side constitute a capacitor or an inductor.

5. The solid-state imaging device according to claim 1, wherein

the first through-electrodes that electrically connect between the power supply line and the first wiring layer are arranged so that potential of the power supplied to the peripheral circuit is constant over the peripheral region.

6. The solid-state imaging device according to claim 1, wherein

the first wiring layer is formed in a plane form and covers at least part of the peripheral circuit region.

7. The solid-state imaging device according to claim 1, wherein

the peripheral circuit region comprises an analog circuit region in which an analog circuit is provided and a logic circuit region in which a logic circuit is provided,

the first through-electrodes that electrically connect between the power supply line and the first wiring layer are provided in both the analog circuit region and the logic circuit region.

8. The solid-state imaging device according to claim 1, further comprising:

a power supply pad provided at the second side and at outside of the peripheral circuit region, wherein

the power supply pads receives the electric power from outside and supplies the received electric power to the first wiring layer.

9. The solid-state imaging device according to claim 1, further comprising:

first and second signal lines to supply a processing signal, provided at the first side of the semiconductor element layer in the peripheral circuit region;

a second wiring layer provided at the second side of the semiconductor element layer in the peripheral circuit region; and

third and fourth through-electrodes provided in the peripheral circuit region and passing through the semiconductor element layer between the first side and the second side, wherein

the third through-electrode electrically connects the first signal line and the second wiring layer and the fourth through-electrode electrically connects the second signal line and the second wiring layer.

10. The solid-state imaging device according to claim 1, wherein

the second side is a light incident side of the photodiodes.

11. A method for supplying an electric power to a peripheral circuit of a solid-state imaging device that has a semiconductor element layer having a pixel region in which a plurality of photodiodes are provided and a peripheral circuit region in which the peripheral circuit for processing of signals generated from the pixels is provided, the method comprising:

supplying the electric power from a first side of the semiconductor element layer to the peripheral circuit;

supplying the electric power from a second side of the semiconductor element layer to the first side of the semiconductor element layer through a plurality of through-electrodes provided in the peripheral circuit region; and

supplying the electric power from outside of the peripheral circuit region to the peripheral circuit region at the second side of the semiconductor element layer.

12. The method according to claim 11, further comprising:

supplying the electric power from outside of the peripheral circuit region and at the second side of the semiconductor element layer to the peripheral circuit through a through-electrode provided at the outside of the peripheral circuit region.

13. The method according to claim 11, wherein

the electric power is supplied so that potential of the electric power supplied to the peripheral circuit is constant over the peripheral region.

14. The method according to claim 11, wherein

the peripheral circuit region comprises an analog circuit region in which an analog circuit is provided and a logic circuit region in which a logic circuit is provided,

the electric power is supplied so that potential of the electric power supplied to the analog circuit is constant over the analog circuit region.

15. The method according to claim 11, wherein

the peripheral circuit region comprises an analog circuit region in which an analog circuit is provided and a logic circuit region in which a logic circuit is provided,

the electric power is supplied so that potential of the electric power supplied to the logic circuit is constant over the logic circuit region.